| Commit message (Collapse) | Author | Age | Files | Lines |
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Implement by adding the following cases to
ir_exporession::constant_expression_value():
- ir_binop_bit_and
- ir_binop_bit_or
- ir_binop_bit_xor
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Implement by adding the following cases to
ir_expression::constant_expression_value():
- ir_binop_lshfit
- ir_binop_rshfit
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Implement by adding a case to ir_expression::constant_expression_value()
for ir_unop_bit_not.
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Implement by adding the following cases to ast_expression::hir():
- ast_lshift
- ast_rshift
Also, implement ir validation for the new operators by adding the following
cases to ir_validate::visit_leave():
- ir_binop_lshift
- ir_binop_rshift
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Commit for generated file glsl_lexer.cpp follows this commit.
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On evergreen, interpolation has moved into the fragment shader,
with the interpolation parmaters being passed via GPRs and LDS entries.
This works out the number of interps required and reserves GPR/LDS
storage for them, it also correctly routes face/position values which
aren't interpolated from the vertex shader.
Also if we noticed nothing is to be interpolated we always setup perspective
interpolation for one value otherwise the GPU appears to lockup.
This fixes about 15 piglit tests on evergreen.
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Previously _LinkedShaders was a compact array of the linked shaders
for each shader stage. Now it is arranged such that each slot,
indexed by the MESA_SHADER_* defines, refers to a specific shader
stage. As a result, some slots will be NULL. This makes things a
little more complex in the linker, but it simplifies things in other
places.
As a side effect _NumLinkedShaders is removed.
NOTE: This may be a candidate for the 7.9 branch. If there are other
patches that get backported to 7.9 that use _LinkedShader, this patch
should be cherry picked also.
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I broke it in 06fd639c519214b6ebcbf29127b6d9ed429f8641 by only testing
2 generations of hardware :(
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Disabling address printing is helpful for diffing.
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These were left-over bits from when convolution was removed.
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This implements round() via the ir_unop_round_even opcode, rather than
adding a new opcode. We may wish to add one in the future, since it
might enable a small performance increase on some hardware, but for now,
this should suffice.
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Implemented using the op-code introduced in the previous commit.
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Also, update ir_to_mesa's "1.30 is unsupported" case to "handle" it.
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This was being classed as unsupported in one place but used in others.
Enabling it seems to work fine.
Signed-off-by: Dave Airlie <[email protected]>
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Tested with demos/pixeltest - line rasterization doesn't seem to be
set up for GL conventions yet, but at least width is respected now.
Signed-off-by: Dave Airlie <[email protected]>
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Would try to destroy radeon->cman, radeon->kman both which were still
NULL.
Signed-off-by: Dave Airlie <[email protected]>
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Hopefully this code can just go away soon.
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It is now to the point where we have no regressing piglit tests. It
also fixes Yo Frankie! and Humus DynamicBranching, probably due to the
piglit bias tests that work that didn't on the Mesa IR backend.
As a downside, performance takes about a 5-10% performance hit at the
moment (e.g. nexuiz 19.8fps -> 18.8fps), which I plan to resolve by
reintroducing 16-wide fragment shaders where possible. It is a win,
though, for fragment shaders using flow control.
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Simply using RNDU, RNDZ, or RNDE does not produce the desired result.
Rather, the RND* instructions place a value in the destination register
that may be 1 less than the correct answer. They can also set per-channel
"increment bits" in a flag register, which, if set, mean dest needs to
be incremented by 1. A second instruction - a predicated add -
completes the job.
Notably, RNDD always produces the correct answer in a single
instruction.
Fixes piglit test glsl-fs-trunc.
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The existing code used RNDD, which rounds down, rather than toward zero.
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Fixes piglit test glsl-fs-ceil.
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This cuts usually 2 out of 3 instructions for flag reg generation (if
statements, conditional assignment) by producing the conditional mod
in the expression representing the boolean value.
Fixes glsl-fs-vec4-indexing-temp-dst-in-nested-loop-combined (register
allocation no longer fails for the conditional generation
proliferation)
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This will be a place to peephole comparisions directly to the flag
regs, and for now avoids using MOV with conditional mod on gen6, which
is now illegal.
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GLES1 and GLES2 install their own exec pointers and don't need the
Save table. Also, the SET_* macros use different indices for the different
APIs so the offsets used in vtxfmt.c are actually wrong for the ES APIs.
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Improves nexuiz performance 0.91% (+/- 0.54%, n=8)
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So far, I've only seen this be a valgrind warning and not a real failure.
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Just always check for FLUSH_UPDATE_CURRENT and call Driver.BeginVertices
when necessary. By using the unlikely() macros, this ends up as
a 10% performance improvement (for isosurf, anyway) over the old,
complicated function pointer swapping.
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i915g would dereference the NULL pointer.
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Drop the use of SET_CONFIG_ATTRIB. Fix the value of EGL_SAMPLE_BUFFERS
along the way.
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Replace SET_CONFIG_ATTRIB/GET_CONFIG_ATTRIB by direct dereferences.
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This makes _EGLConfig more accessible and scales better when new
attributes are added.
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TGSI tells us when to use this, its not hooked up from GLSL to MESA to TGSI yet though.
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This reverts commit 73dab75b4165f7d2214a68d4ba8e3cb7aab9b4ac.
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Don't use r0 for FF_SYNC dest reg on Sandybridge, which would
smash FFID field in GS payload, that cause later URB write fail.
Also not use r0 in any URB write requiring allocate.
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Signed-off-by: Dave Airlie <[email protected]>
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