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* freedreno/ir3: split out a4xx+ instructionsRob Clark2019-02-167-332/+394
* freedreno/ir3: split out image helpersRob Clark2019-02-166-183/+253
* freedreno/a6xx: clean up some open-coded bitsRob Clark2019-02-161-2/+4
* freedreno/a6xx: move stream-out emit to helperRob Clark2019-02-161-64/+72
* freedreno/ir3: fix varying packing vs. tex sharp edgeRob Clark2019-02-161-2/+30
* radv: fix invalid element type when filling vertex input default valuesSamuel Pitoiset2019-02-161-1/+3
* i965: Removed the field etc_format from the struct intel_mipmap_treeEleni Maria Stea2019-02-153-18/+1
* i965: Enabled the OES_copy_image extension on Gen 7 GPUsEleni Maria Stea2019-02-151-4/+12
* i965: Fixed the CopyImageSubData for ETC2 on Gen < 8Eleni Maria Stea2019-02-153-18/+6
* i965: Faking the ETC2 compression on Gen < 8 GPUs using two miptrees.Eleni Maria Stea2019-02-153-69/+134
* i965: Rename intel_mipmap_tree::r8stencil_* -> ::shadow_*Nanley Chery2019-02-153-19/+19
* nir: remove simple dead if detection from nir_opt_dead_cf()Timothy Arceri2019-02-161-7/+2
* swr/rast: Add translation support to streamoutAlok Hota2019-02-1512-37/+106
* swr/rast: simdlib cleanup, clipper stack space fixesAlok Hota2019-02-1513-135/+127
* swr/rast: convert DWORD->uint32_t, QWORD->uint64_tAlok Hota2019-02-155-25/+25
* swr/rast: Refactor scratch space variable namesAlok Hota2019-02-154-14/+14
* swr/rast: FP consistency between POSH/RENDER pipesAlok Hota2019-02-154-11/+33
* swr/rast: Move knob defaults to generated cpp fileAlok Hota2019-02-152-7/+14
* swr/rast: Flip BitScanReverse index calculationAlok Hota2019-02-151-2/+2
* swr/rast: Correctly align 64-byte spills/fillsAlok Hota2019-02-151-2/+2
* swr/rast: Disable use of __forceinline by defaultAlok Hota2019-02-151-1/+12
* swr/rast: Convert system memory pointers to gfxptr_tAlok Hota2019-02-156-3/+18
* radv: Use correct num formats to detect whether we should be use 1.0 or 1.Bas Nieuwenhuizen2019-02-151-1/+2
* nir/algebraic: Simplify comparison with sequential integers starting with 0Ian Romanick2019-02-151-0/+5
* nir/algebraic: Convert some f2u to f2iIan Romanick2019-02-151-0/+13
* intel/compiler/test: Add unit test for mismatched signedness comparisonMatt Turner2019-02-151-0/+32
* intel/compiler: Avoid propagating inequality cmods if types are differentMatt Turner2019-02-151-0/+7
* intel/compiler/test: Set devinfo->gen = 7Matt Turner2019-02-151-1/+1
* gallium/auxiliary/vl: Add video compositor compute shader renderJames Zhu2019-02-152-28/+83
* gallium/auxiliary/vl: Add compute shader to support video compositor renderJames Zhu2019-02-155-0/+469
* gallium/auxiliary/vl: Rename csc_matrix and increase its size.James Zhu2019-02-153-7/+7
* gallium/auxiliary/vl: Split vl_compositor graphic shaders from vl_compositor APIJames Zhu2019-02-155-688/+821
* gallium/auxiliary/vl: Move dirty define to header fileJames Zhu2019-02-152-9/+8
* nir: remove jump from two merging jump-ending blocksJuan A. Suarez Romero2019-02-151-2/+19
* nir: move ALU instruction before the jump instructionJuan A. Suarez Romero2019-02-151-1/+1
* mesa: INVALID_VALUE for wrong type or format in Clear*Buffer*DataAndres Gomez2019-02-151-4/+6
* virgl: use virgl_transfer_inline_write even lessGurchetan Singh2019-02-151-1/+1
* virgl: use transfer queueGurchetan Singh2019-02-155-18/+36
* virgl: introduce transfer queueGurchetan Singh2019-02-155-0/+390
* virgl: add encoder functions for new protocolGurchetan Singh2019-02-152-0/+28
* virgl: make winsys modifications for encoded transfersGurchetan Singh2019-02-155-6/+21
* virgl: add extra checks in virgl_res_needs_flush_waitGurchetan Singh2019-02-151-4/+9
* virgl: pass virgl transfer to virgl_res_needs_flush_waitGurchetan Singh2019-02-155-14/+22
* virgl: keep track of number of computationsGurchetan Singh2019-02-152-3/+3
* virgl: limit command length to 16 bitsGurchetan Singh2019-02-152-5/+8
* virgl: use virgl_transfer in inline writeGurchetan Singh2019-02-151-26/+40
* virgl: add protocol for resource transfersGurchetan Singh2019-02-152-0/+12
* virgl: when creating / freeing transfers, pass slab pool directlyGurchetan Singh2019-02-154-14/+14
* virgl: unmap uploader at flush timeGurchetan Singh2019-02-151-2/+3
* virgl: make alignment smaller when uploading index user buffersGurchetan Singh2019-02-151-1/+1
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