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* anv: fix VkExternalBufferProperties for unsupported handlesChia-I Wu2019-07-071-1/+7
* radv: Handle cmask being disallowed by addrlib.Bas Nieuwenhuizen2019-07-071-0/+5
* radv/gfx10: enable support for NAVI10, NAVI12 and NAVI14Samuel Pitoiset2019-07-071-3/+0
* radv/gfx10: Use GS rectlist when needed.Bas Nieuwenhuizen2019-07-071-0/+2
* radv/gfx10: implement NGG support (VS only)Samuel Pitoiset2019-07-076-22/+610
* radv: Combine vs and tes output keys parts.Bas Nieuwenhuizen2019-07-074-46/+48
* radv/gfx10: Use new uconfig reg index packet for GFX10+.Bas Nieuwenhuizen2019-07-074-6/+18
* radv/gfx10: Set MEM_ORDERED flags on shaders.Bas Nieuwenhuizen2019-07-071-0/+9
* radv/gfx10: emit GE_CNTL instead of IA_MULTI_VGT_PARAM for legacy modeSamuel Pitoiset2019-07-072-4/+44
* radv/gfx10: double the number of tessellation offchip buffers per SESamuel Pitoiset2019-07-071-3/+5
* radv/gfx10: require LLVM 9+Samuel Pitoiset2019-07-071-0/+6
* radv/gfx10: disable geometry and tessellation shadersSamuel Pitoiset2019-07-071-2/+2
* radv/gfx10: disable binningSamuel Pitoiset2019-07-071-1/+2
* radv/gfx10: disable CLEAR_STATESamuel Pitoiset2019-07-072-5/+2
* radv/gfx10: disable VK_EXT_transform_feedbackSamuel Pitoiset2019-07-071-1/+1
* radv/gfx10: set user data base registersSamuel Pitoiset2019-07-071-17/+26
* radv/gfx10: add gfx10_cs_emit_cache_flushSamuel Pitoiset2019-07-071-1/+174
* radv/gfx10: set the DCC constant encoding flagSamuel Pitoiset2019-07-071-1/+2
* radv/gfx10: do not declare streamout SGPRSSamuel Pitoiset2019-07-071-0/+3
* radv/gfx10: do not set stream output shader configSamuel Pitoiset2019-07-071-7/+7
* radv/gfx10: emit VGT_VERTEX_REUSE_BLOCK_CNTL during gfx initializationSamuel Pitoiset2019-07-072-1/+3
* radv/gfx10: update shader-related fields in si_emit_graphics()Samuel Pitoiset2019-07-071-0/+13
* radv/gfx10: implement si_emit_compute()Samuel Pitoiset2019-07-071-1/+5
* radv/gfx10: mask DCC tile swizzle by alignmentSamuel Pitoiset2019-07-071-1/+4
* radv/gfx10: initialize GE_{MAX,MIN}_VTX_INDX/INDX_OFFSETSamuel Pitoiset2019-07-071-1/+5
* radv/gfx10: implement radv_flush_vertex_descriptors() changeSamuel Pitoiset2019-07-071-3/+10
* radv/gfx10: implement fill_geom_tess_rings()Samuel Pitoiset2019-07-071-20/+57
* radv/gfx10: implement radv_CmdBindDescriptorSets()Samuel Pitoiset2019-07-071-3/+11
* radv/gfx10: implement write_buffer_descriptor()Samuel Pitoiset2019-07-071-3/+10
* radv/gfx10: use the correct register for image descriptor dumpingSamuel Pitoiset2019-07-071-2/+5
* radv/gfx10: implement radv_pipeline_generate_hw_hs()Samuel Pitoiset2019-07-071-5/+18
* radv/gfx10: implement radv_fill_shader_variant()Samuel Pitoiset2019-07-071-2/+7
* radv/gfx10: implement radv_pipeline_generate_geometry_shader()Samuel Pitoiset2019-07-071-3/+9
* radv/gfx10: implement radv_init_sampler()Samuel Pitoiset2019-07-071-6/+13
* radv/gfx10: fix PS exports for SPI_SHADER_32_ARSamuel Pitoiset2019-07-071-3/+9
* radv/gfx10: implement radv_get_device_name()Samuel Pitoiset2019-07-071-0/+3
* radv/gfx10: set RADV_FORCE_FAMILYSamuel Pitoiset2019-07-071-1/+3
* radv/gfx10: fix a possible hang with exp pos0 with done=0 and exec=0Samuel Pitoiset2019-07-071-0/+8
* radv/gfx10: set PA_SC_TILE_STEERING_OVERRIDESamuel Pitoiset2019-07-071-0/+2
* radv/gfx10: set cache control registersSamuel Pitoiset2019-07-071-0/+21
* radv/gfx10: set llvm_has_working_vgpr_indexingSamuel Pitoiset2019-07-071-3/+2
* radv/gfx10: update DB_DFSM_CONTROL registerSamuel Pitoiset2019-07-071-2/+8
* radv/gfx10: update DB_Z_INFO registerSamuel Pitoiset2019-07-071-2/+2
* radv/gfx10: implement radv_emit_global_shader_pointers()Samuel Pitoiset2019-07-071-1/+11
* radv/gfx10: implement radv_emit_tess_factor_ring()Samuel Pitoiset2019-07-071-1/+5
* radv/gfx10: implement radv_emit_fb_ds_state()Samuel Pitoiset2019-07-071-2/+20
* radv/gfx10: implement radv_initialise_ds_surface()Samuel Pitoiset2019-07-072-10/+25
* radv/gfx10: implement radv_emit_fb_color_state()Samuel Pitoiset2019-07-071-1/+30
* radv/gfx10: implement radv_initialise_color_surface()Samuel Pitoiset2019-07-072-11/+28
* radv/gfx10: implement radv_init_dcc_control_reg()Samuel Pitoiset2019-07-071-22/+32
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