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* nir: Transform pow(x, 4) into (x*x)*(x*x).Matt Turner2015-04-241-0/+1
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* glsl: Transform pow(x, 4) into (x*x)*(x*x).Matt Turner2015-04-241-0/+20
| | | | | Reviewed-by: Juha-Pekka Heikkila <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* mesa: fix glGetActiveUniformsiv regressionTapani Pälli2015-04-241-4/+16
| | | | | | | | | | | Commit 7519ddb caused regression to glGetActiveUniformsiv. Patch adds back validation loop of all given uniforms before writing any values, not touching params in case of errors is tested by the conformance suite. Signed-off-by: Tapani Pälli <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90149 Reviewed-by: Martin Peres <[email protected]>
* mesa: refactor active attrib queries for glGetProgramivTapani Pälli2015-04-241-25/+14
| | | | | | | | | | | | | | | Main motivation here is to get rid of iterating IR and encapsulate queries within program resources. No functional changes. Piglit tests calling the modified functionality: - gl-get-active-attrib-returns-all-inputs - glsl-1.50-get-active-attrib-array - getactiveattrib Signed-off-by: Tapani Pälli <[email protected]> Reviewed-by: Martin Peres <[email protected]>
* i965: Add an INTEL_DEBUG=spill option to test spillingJason Ekstrand2015-04-233-1/+3
| | | | | Reviewed-by: Jordan Justen <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965/debug: Use the ull specifier for DEBUG enum definesJason Ekstrand2015-04-231-31/+31
| | | | | | | The INTEL_DEBUG variable is a uint64_t and if we want a enum value higer than 32 bits, you need to use ull. We might as well use it for all of them. Reviewed-by: Matt Turner <[email protected]>
* i965: Disallow linear blits that are not cacheline aligned.Kenneth Graunke2015-04-231-8/+19
| | | | | | | | | | | | | | | The BLT engine on Gen8+ requires linear surfaces to be cacheline aligned. This restriction was added as part of converting the BLT to use 48-bit addressing. The main user, intel_emit_linear_blit, now handles this properly. But we might also have linear miptrees; just refuse to blit those. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=88521 Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Anuj Phogat <[email protected]> Cc: [email protected]
* i965: Make intel_emit_linear_blit handle Gen8+ alignment restrictions.Kenneth Graunke2015-04-231-8/+14
| | | | | | | | | | | | | | | | | | | | The BLT engine on Gen8+ requires linear surfaces to be cacheline aligned. This restriction was added as part of converting the BLT to use 48-bit addressing. intel_emit_linear_blit needs to handle blits that are not cacheline aligned, as we use it for arbitrary glBufferSubData calls and subrange mappings. Since intel_emit_linear_blit uses 1 byte per pixel, we can use the src/dst pixel X offset field to represent the unaligned portion, and subtract that from the address so it's cacheline aligned. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=88521 Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Anuj Phogat <[email protected]> Cc: [email protected]
* mapi: Adding missing string.h include.Pali Rohár2015-04-231-0/+2
| | | | | | | | File glapi_entrypoint.c calls memcpy() function, but does not include string.h header. So compilation can fail at error: implicit declaration of function 'memcpy'. Signed-off-by: Jose Fonseca <[email protected]>
* os/os_memory_aligned.h: Handle integer overflow.Jose Fonseca2015-04-231-1/+27
| | | | | | | | | | | This code is only used when our memory debugging wrappers are enabled, as we use the C runtime functions directly elsewhere. Tested llvmpipe on Windows w/ memory debugging enabled. VMware PR894263. Reviewed-by: Roland Scheidegger <[email protected]>
* draw: fix prim ids when there's no gsRoland Scheidegger2015-04-233-2/+15
| | | | | | | | | | | | | | | We were resetting the prim id count for each run of the prim assembler, hence this only worked when the draw calls were very small (the exact limit depending on the vertex size), since larger draw calls get split up. So, do the same as we do already if there's a gs, reset it to zero explicitly for every new instance (this possibly could use the same variable but that isn't doable without some heavy refactoring and I'm not sure it makes sense). Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90130. Reviewed-by: Jose Fonseca <[email protected]> CC: <[email protected]>
* gallium/radeon: don't crash when getting out-of-bounds TEMP referencesMarek Olšák2015-04-231-0/+6
| | | | Reviewed-by: Tom Stellard <[email protected]>
* nir/lower_source_mods: Don't propagate register sourcesJason Ekstrand2015-04-221-0/+7
| | | | | | | | | The nir_lower_source_mods pass does a weak form of copy propagation to clean up all of the mov-with-negate's that get generated. However, we weren't properly checking that the sources were SSA and so we could end up moving a register read which is not, in general, valid. Reviewed-by: Connor Abbott <[email protected]>
* nir: Rewrite instr_rewrite_srcJason Ekstrand2015-04-221-24/+28
| | | | | | | The old code wasn't correctly handling the case where the new value of the source contains an indirect. Reviewed-by: Connor Abbott <[email protected]>
* nir/locals_to_regs: Hanadle indirect accesses of length-1 arraysJason Ekstrand2015-04-221-0/+8
| | | | Reviewed-by: Connor Abbott <[email protected]>
* nir/locals_to_regs: Initialize registers with constant initializersJason Ekstrand2015-04-221-0/+103
| | | | Reviewed-by: Connor Abbott <[email protected]>
* nir/locals_to_regs: Pass around the nir_shader rather than a void * mem_ctxJason Ekstrand2015-04-221-13/+13
| | | | Reviewed-by: Connor Abbott <[email protected]>
* nir: Add a simple growing array data structureJason Ekstrand2015-04-221-0/+96
| | | | Reviewed-by: Connor Abbott <[email protected]>
* nir/types: Make glsl_get_length smarterJason Ekstrand2015-04-224-55/+8
| | | | | | | | | | | | | | | | | | Previously, this function returned the number of elements for structures and arrays and 0 for everything else. In NIR, this is almost never what you want because we also treat matricies as arrays so you have to special-case constantly. This commit glsl_get_length treat matrices as an array of columns by returning the number of columns instead of 0 This also fixes a bug in locals_to_regs caused by not checking for the matrix case in one place. v2: Only special-case for matrices and return a length of 0 for vectors as we did before. This was needed to not break the TGSI-based drivers and doesn't really affect NIR at the moment. Reviewed-by: Connor Abbott <[email protected]> Tested-by: Rob Clark <[email protected]>
* nir: Move get_const_initializer_load from vars_to_ssa to NIR coreJason Ekstrand2015-04-223-62/+65
| | | | Reviewed-by: Connor Abbott <[email protected]>
* nir/lower_vars_to_ssa: Pass around the nir_shader instead of a void mem_ctxJason Ekstrand2015-04-221-14/+14
| | | | Reviewed-by: Connor Abbott <[email protected]>
* i965/nir: Use the correct offsets when handling register indirectsJason Ekstrand2015-04-221-27/+27
| | | | Reviewed-by: Connor Abbott <[email protected]>
* nir/print: Print the closing paren on load_const instructionsJason Ekstrand2015-04-221-0/+2
| | | | Reviewed-by: Connor Abbott <[email protected]>
* nir/tex: Use the correct return size for query_levels and lodJason Ekstrand2015-04-221-1/+4
| | | | Reviewed-by: Connor Abbott <[email protected]>
* nir: Refactor tex_instr_dest_size to use a switch statementJason Ekstrand2015-04-221-5/+8
| | | | Reviewed-by: Connor Abbott <[email protected]>
* nir/lower_vars_to_ssa: Actually look for indirects when determining aliasingJason Ekstrand2015-04-221-0/+4
| | | | Reviewed-by: Connor Abbott <[email protected]>
* st/mesa: add ARB_texture_stencil8 support (v4)Dave Airlie2015-04-234-16/+22
| | | | | | | | | | | | | | | | | | if we support stencil texturing, enable texture_stencil8 there is no requirement to support native S8 for this, the texture can be converted to x24s8 fine. v2: fold fixes from Marek in: a) put S8 last in the list b) fix renderable to always test for d/s renderable fixup the texture case to use a stencil only format for picking the format for the texture view. v3: hit fallback for getteximage v4: put s8 back in front, it shouldn't get picked now (Ilia) Reviewed-by: Ilia Mirkin <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* mesa: finish implementing ARB_texture_stencil8 (v5)Dave Airlie2015-04-234-5/+58
| | | | | | | | | | | | | | Parts of this were implemented previously, so finish it off. v2: fix getteximage falling into the integer check add fixes for the FBO paths, (fbo-stencil8 test). v3: fix getteximage path harder. v4: remove swapbytes from getteximage path (Ilia) v5: brown paper bag the swapbytes removal. (Ilia) Reviewed-by: Ilia Mirkin <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* mesa: remove the gl_sl_pragmas structureJason Ekstrand2015-04-223-22/+0
| | | | | | | This code was added by Brian Paul in 2009 but, as far as Matt and I can tell, it's been dead ever since the new GLSL compiler was added. Reviewed-by: Brian Paul <[email protected]>
* i965: Add a brw_compiler structure and store the register sets in itJason Ekstrand2015-04-227-97/+120
| | | | Reviewed-by: Matt Turner <[email protected]>
* i965: Rename brw_compile to brw_codegenJason Ekstrand2015-04-2229-246/+246
| | | | | | | | | | | | This name better matches what it's actually used for. The patch was generated with the following command: for file in *; do sed -i -e s/brw_compile/brw_codegen/g $file done Signed-off-by: Jason Ekstrand <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965: Use device_info instead of the context for computing vue mapsJason Ekstrand2015-04-224-7/+12
| | | | Reviewed-by: Matt Turner <[email protected]>
* i965: Use device_info instead of the context in instruction schedulingJason Ekstrand2015-04-223-14/+13
| | | | Reviewed-by: Matt Turner <[email protected]>
* i965: Add a devinfo field to backend_visitor and use it for gen checksJason Ekstrand2015-04-2219-221/+225
| | | | Reviewed-by: Matt Turner <[email protected]>
* i965: Remove remaining uses of ctx->Const.UniformBooleanTrue in visitorsJason Ekstrand2015-04-222-12/+6
| | | | | | | | | | Since commit 2881b123, we have used 0/~0 for representing booleans on all gens. However, we still had a bunch of places in the visitor code where we were still referring to ctx->Const.UniformBooleanTrue. Since this is always ~0, we can just remove them. Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965/vec4: Add a devinfo field to the generator and use it for gen checksJason Ekstrand2015-04-222-46/+42
| | | | Reviewed-by: Matt Turner <[email protected]>
* i965/fs: Add a devinfo field to the generator and use it for gen checksJason Ekstrand2015-04-222-59/+58
| | | | Reviewed-by: Matt Turner <[email protected]>
* i965/device_info: Add a supports_simd16_3src flagJason Ekstrand2015-04-226-55/+56
| | | | | | | | | | This also involves moving revision checking to screen creation time and passing that into brw_get_device_info so that we can get the right device_info for early versions of SKL. Since the only place we used revision was to check for SIMD16 3-src instruction support, it's safe to remove the revision field from brw_context. Reviewed-by: Matt Turner <[email protected]>
* i965/device_info: Add a HSW_FEATURES macroJason Ekstrand2015-04-221-3/+7
| | | | | | It's basically just a copy of GEN7_FEATURES only with is_haswell set Reviewed-by: Matt Turner <[email protected]>
* i965: Make the annotation code take a device_info instead of a contextJason Ekstrand2015-04-224-10/+14
| | | | Reviewed-by: Matt Turner <[email protected]>
* i965/fs: Remove the GL context from the generatorJason Ekstrand2015-04-222-11/+1
| | | | Reviewed-by: Matt Turner <[email protected]>
* i965: Remove the context field from brw_compilerJason Ekstrand2015-04-2215-63/+42
| | | | Reviewed-by: Matt Turner <[email protected]>
* i965: Make the disassembler take a device_info instead of a contextJason Ekstrand2015-04-2211-109/+99
| | | | Reviewed-by: Matt Turner <[email protected]>
* i965: Make instruction compaction take a device_info instead of a contextJason Ekstrand2015-04-224-109/+112
| | | | Reviewed-by: Matt Turner <[email protected]>
* i965: Make the brw_inst helpers take a device_info instead of a contextJason Ekstrand2015-04-2216-995/+1006
| | | | Reviewed-by: Matt Turner <[email protected]>
* i965/eu: Add a devinfo parameter to brw_compileJason Ekstrand2015-04-222-0/+2
| | | | Reviewed-by: Matt Turner <[email protected]>
* i965: Do better fake context setup in unit testsJason Ekstrand2015-04-225-5/+24
| | | | | | | In future tests, we will start relying on devinfo and not just brw in the compiler. Changing this now keeps these tests from failing in the future. Reviewed-by: Matt Turner <[email protected]>
* i965: Remove the context parameter from brw_texture_offsetJason Ekstrand2015-04-225-12/+5
| | | | | | | | It wasn't really being used anyway. We used it to assert that gpu_shader5 is supported in the back-end but that should be caught by the front-end. Signed-off-by: Jason Ekstrand <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* softpipe: fix stencil write to use an integer valueDave Airlie2015-04-231-1/+1
| | | | | | | | | | | This fixes a number of regressions since 61393bdcdc3b63624bf6e9730444f5e9deeedfc8 u_tile: fix stencil texturing tests under softpipe Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89960 Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Roland Scheidegger <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* mesa: Fix typo in a commentAnuj Phogat2015-04-221-2/+2
| | | | | Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Brian Paul <[email protected]>
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