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* util: disable cache if we have no build-id and timestamp is zeroTimothy Arceri2018-10-022-4/+9
| | | | | | | | | | Timestamp can be zero for example when Flatpak is used. In this case just disable the cache rather then segfaulting when incompatible cache items are loaded. V2: actually return false when mtime is 0. Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radeonsi: add a workaround for bitfield_extract when count is 0Timothy Arceri2018-10-021-11/+30
| | | | | | | | | | | | | | | This ports the fix from 3d41757788ac. Both LLVM 7 & 8 continue to have this problem. It fixes rendering issues in some menu and loading screens of Civ VI which can be seen in the trace from bug 104602. Note: This does not fix the black triangles on Vega for bug 104602. Reviewed-by: Marek Olšák <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104602 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107276
* anv: Implement VK_KHR_driver_propertiesJason Ekstrand2018-10-012-0/+24
| | | | Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* vulkan: Update the XML and headers to 1.1.86Jason Ekstrand2018-10-011-66/+791
| | | | Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: do not try to set DCC_CONTROL when image doesn't use DCCSamuel Pitoiset2018-10-011-1/+1
| | | | | | | | Unnecessary. While we are at it, remove the check for pre-VI because it's already checked earlier. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: add a sanity check for mutable formats and TC-compat HTILESamuel Pitoiset2018-10-011-5/+22
| | | | | | | | | | If apps use the MUTABLE bit and the same formats as the image one in the list, we can still enable TC-compat HTILE. I don't think this happens often but given the fact that TC-compat HTILE allows a nice boost in some situations, it's worth checking. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: disable HTILE for very small depth surfacesSamuel Pitoiset2018-10-011-1/+3
| | | | | | | | | | | Like we disable DCC/CMASK for small color surfaces as well. Serious Sam 2017 creates a 1x1 depth surface and I think it should be faster to do slow clears on the graphics queue instead of fast clears on compute, and eventually a depth expand if the surface isn't TC-compatible HTILE. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: add potential missing fields for DB_EQAASamuel Pitoiset2018-10-011-1/+3
| | | | | | | Other drivers set these two as well, just apply the same rule. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: disable complicated point clipping against user clip planesSamuel Pitoiset2018-10-011-1/+0
| | | | | | | | | I don't think this is required by Vulkan too. Ported from RadeonSI (AMDVLK doesn't set it either). Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* gallium/util: Clarify comment in util_init_thread_pinningMichel Dänzer2018-09-281-1/+4
| | | | | | | | | | As discussed in the review of the patch which added the comment: Nothing happens when a thread is created, because pthread_atfork doesn't affect creating threads. However, spawning a child process will likely crash. Reviewed-by: Marek Olšák <[email protected]>
* radv: do not sync CP DMA when copying buffersSamuel Pitoiset2018-09-281-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We already track if the DMA engine is busy/idle with a flag, and we emit a packet that waits for all CP DMA operations to be complete. This is done at end of command buffer because the kernel doesn't wait for them, and also when emitting barriers, so it should be safe. This improves small copies for both aligned and unaligned sizes. Aligned sizes: BEFORE: 1 KB: 59.840000 ms 2 KB: 71.200000 ms AFTER: 1 KB: 31.200000 ms 2 KB: 31.040000 ms Unaligned sizes: BEFORE: 2 KB: 68.3200 ms 3 KB: 79.3600 ms 5 KB: 76.6400 ms 9 KB: 90.8800 ms 17 KB: 116.0000 ms AFTER: 2 KB: 31.0400 ms 3 KB: 32.0000 ms 5 KB: 30.8800 ms 9 KB: 30.5600 ms 17 KB: 29.6000 ms Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: adjust the CmdUpdateBuffer threshold for optimal performanceSamuel Pitoiset2018-09-282-1/+3
| | | | | | | | | | | | | | | | According to my benchmark results, it appears that we should reduce the threshold to 1024. BEFORE: 1 KB: 68.656000 ms 2 KB: 118.368000 ms AFTER: 1 KB: 31.760000 ms 2 KB: 29.840000 ms Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: do not use the availability bit for timestamp queriesSamuel Pitoiset2018-09-282-30/+28
| | | | | | | | | | | It's unnecessary because we can just check if the timestamp is to different to the default value when a pool is created or resetted. Instead of waiting for the availability bit to be 1, we have to emit a not equal WAIT_REG_MEM for checking if the timestamp is ready. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* freedreno/a6xx: Build up draw dword0 outside visibilty if statementKristian H. Kristensen2018-09-271-17/+18
| | | | | | | | Pulling this logic out means we can share the logic and avoid a couple of temporary variables that helped make things clearer before. Note that in either vismode case, we always program vismode 0. Signed-off-by: Kristian H. Kristensen <[email protected]>
* freedreno/a6xx: Simplify draw_emit() branches a bitKristian H. Kristensen2018-09-271-16/+8
| | | | | | | | Now that we've copied the emit logic into each branch of the if (info->index_size) statement, we can simplify the logic a bit according to which case we're in. Signed-off-by: Kristian H. Kristensen <[email protected]>
* freedreno/a6xx: Copy OUT_RING() part into each branch of the index ifKristian H. Kristensen2018-09-271-17/+29
| | | | Signed-off-by: Kristian H. Kristensen <[email protected]>
* freedreno/a6xx: Split fd6_draw_emit into direct and indirect pathsKristian H. Kristensen2018-09-271-36/+46
| | | | | | | This splits the two code paths into separate functions and moves the "if (info->indirect)" test into draw_impl(). Signed-off-by: Kristian H. Kristensen <[email protected]>
* freedreno/a6xx: Inline fd6_draw()Kristian H. Kristensen2018-09-271-31/+17
| | | | | | Simplify the code a bit by inlining this helper. Signed-off-by: Kristian H. Kristensen <[email protected]>
* freedreno/a6xx: Move emit_marker and wfi to draw_impl()Kristian H. Kristensen2018-09-271-17/+12
| | | | | | | This way the markers clearly bracket the draw call and isn't duplicated for both direct and indirect draw code. Signed-off-by: Kristian H. Kristensen <[email protected]>
* freedreno/a6xx: Move inline functions out of fd6_draw.hKristian H. Kristensen2018-09-273-108/+110
| | | | | | Only used in fd6_draw.c so put them there. Signed-off-by: Kristian H. Kristensen <[email protected]>
* freedreno: fix a typo in launch_gridHyunjun Ko2018-09-271-1/+1
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* freedreno/ir3: fix the param order of cmpxchgHyunjun Ko2018-09-271-2/+2
| | | | | | | | | | | According to the following definition, int AtomicCompSwap(inout int mem, uint compare, uint data); the preceding one in atomic_comp_swap of NIR is compare and data is followed, while src0 for cmpxchg needs vec2(data, compare) So for ssbo/image deref comp_swap, that should be reversed. Fixes: dEQP-GLES31.functional.image_load_store.*.atomic.comp_swap*
* freedreno/a6xx: fix shaders w/ >= 24 regsRob Clark2018-09-271-1/+1
| | | | | | | | Possibly these bits mean something else now. Blob always seems to use FOUR_QUADS, and changing to TWO_QUADS seems to cause different threads to overlap registers. Signed-off-by: Rob Clark <[email protected]>
* freedreno/a6xx: fix gl_FragCoord.wRob Clark2018-09-271-2/+6
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno: handle invalidated buffers harderRob Clark2018-09-278-7/+39
| | | | | | Do a better job of skipping mem2gmem/gmem2mem.. Signed-off-by: Rob Clark <[email protected]>
* freedreno/a6xx: fix constlenRob Clark2018-09-271-7/+6
| | | | | | | | | Fix a few bits of confusion, as with previous gen's constlen is aligned to 4, and value in bitfield is left-shifted by 2 (ie. divided by 4). But this is done by the CONSTLEN() accessor/builder fxn, so don't do it twice. Also HLSQ_FS_CNTL.CONSTLEN is not special. Signed-off-by: Rob Clark <[email protected]>
* freedreno: fix inorder rendering caseRob Clark2018-09-271-6/+7
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/a6xx: backface stencil stateRob Clark2018-09-272-2/+4
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/a6xx: fix gpu crash with separate-stencilRob Clark2018-09-271-1/+1
| | | | | | | Fixes a crash in (of all things) dEQP-GLES2.info.vendor with --deqp-surface-type=fbo.. Signed-off-by: Rob Clark <[email protected]>
* freedreno/a6xx: fix MRT configRob Clark2018-09-271-7/+7
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno: fix potential hang when destroying batchRob Clark2018-09-271-1/+1
| | | | | | | batch_flush_reset_dependencies() expects to be called unlocked, and can call fd_batch_reference() which can try to aquire the screen lock again. Signed-off-by: Rob Clark <[email protected]>
* freedreno: fix corrupted fb stateRob Clark2018-09-272-2/+5
| | | | | | | | | | | In c3d9f29b we allowed ctx->batch to be null, and started tracking the current framebuffer state in fd_context. But the existing logic in fd_blitter_pipe_begin() would, if !ctx->batch, set null fb state to be restored after blit. Which broke the world of deqp (and probably other things) Fixes: c3d9f29b781 freedreno: allocate ctx's batch on demand Signed-off-by: Rob Clark <[email protected]>
* freedreno: simplify pctx->clear()Rob Clark2018-09-276-74/+11
| | | | | | | | | | | | This is defined to always clear the entire surface(s) specified, regardless of scissor state.. mesa/st will turn scissored clears into a draw. So rip about a bunch of unnecessary machinery. Also remove a comment that was obsolete since using u_blitter to turn clear into draw (for the cases where there isn't a hw blitter fast-path). Signed-off-by: Rob Clark <[email protected]>
* freedreno: fix FD_MESA_DEBUG=flushRob Clark2018-09-272-2/+8
| | | | | | | The logic to force a flush every draw was short-circuited with newer kernels. Also it should apply to clears as well. Signed-off-by: Rob Clark <[email protected]>
* freedreno: fix scissor state emitRob Clark2018-09-274-4/+8
| | | | | | | The effective scissor changes based on rasterizer->scissor flag, so we need to re-emit scissor state when rasterizer state changes. Signed-off-by: Rob Clark <[email protected]>
* freedreno: update generated headersRob Clark2018-09-278-340/+1089
| | | | Signed-off-by: Rob Clark <[email protected]>
* st/mesa: do not call update_framebuffer_size with NULL pointerErik Faye-Lund2018-09-271-1/+2
| | | | | | | | | | | | | | | | In st_renderbuffer_alloc_storage, we avoid allocating storage for zero-sized buffers, leading to this pointer being NULL. We already take care to avoid dereferencing these pointers for color-buffers, but not for depth/stencil-buffers. So let's thread a bit more carefully here. This avoids a crash while running Piglit's glx/glx-visuals-stencil test, both on virgl and r600g. Signed-off-by: Erik Faye-Lund <[email protected]> Reviewed-by: Guillaume Charifi <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* vulkan: Disable randr lease for libxcb < 1.13Maxime2018-09-271-0/+2
| | | | | | | | | | | Since the Randr lease code was added, compiling against libxcb 1.12 no longer works. CC: [email protected] Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108024 Fixes: 7ab1fffcd2a504024b16e408de329f7a94553ecc Tested-By: Maxime <[email protected]> Fixes: 7ab1fffcd2a504024b16 "vulkan: Add EXT_acquire_xlib_display [v5]"
* radv: Remove garbage comment.Bas Nieuwenhuizen2018-09-271-1/+0
| | | | Trivial.
* radv: Do not use multiple draws for multisample copies.Bas Nieuwenhuizen2018-09-271-57/+5
| | | | | | | | Use sample rate shading instead, should give better locality. Makes Nier with 8x msaa on a Raven go 5 fps -> 7 fps in the menu. Reviewed-by: Samuel Pitoiset <[email protected]>
* anv: If softpin is supported, use it with the hiz clear value boJordan Justen2018-09-261-0/+9
| | | | | | Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Nanley Chery <[email protected]>
* anv: s/batch/value_bo/ on anv_device_init_hiz_clear_batchJordan Justen2018-09-261-2/+2
| | | | | | Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Nanley Chery <[email protected]>
* intel/isl: Add a unit suffixes to some struct fields and variablesJason Ekstrand2018-09-2622-189/+190
| | | | | | | | | | | | | I was about to make the claim to someone that every field in isl_surf is either an enum or has explicit units. Then I looked at isl_surf and discovered this claim was wrong. We should fix that. This commit does a few refactors: * Add _B suffixes to some struct fields * Add _B to some variables and parameters * Rename row_pitch_tiles -> row_pitch_tl Reviewed-by: Nanley Chery <[email protected]>
* radeonsi: NaN should pass kill_ifAxel Davy2018-09-251-1/+2
| | | | | | | | | | | | | | | Fixes: https://bugs.freedesktop.org/show_bug.cgi?id=105333 Fixes: https://github.com/iXit/Mesa-3D/issues/314 For this application, NaN is passed to KILL_IF and is expected to pass. v2: Explain in the code why UGE is used. Signed-off-by: Axel Davy <[email protected]> Reviewed-by: Marek Olšák <[email protected]> CC: <[email protected]>
* st/nine: Do not mark both ff vs and ps updatedAxel Davy2018-09-251-2/+4
| | | | | | | | | | | | | | | | Previously if only ff vs or only ff ps was used, the constants for both were marked as updated, while only the constants of the used ff shader were updated. Now that NINE_STATE_FF_VS and NINE_STATE_FF_PS do not intersect anymore, we can correctly mark the correct set of constant as updated. Fixes: https://github.com/iXit/Mesa-3D/issues/319 Signed-off-by: Axel Davy <[email protected]>
* st/nine: Split NINE_STATE_FF_OTHERAxel Davy2018-09-255-23/+23
| | | | | | | | | | | NINE_STATE_FF_OTHER was mostly ff vs states. Rename it to NINE_STATE_FF_VS_OTHER and move common states with ps to NINE_STATE_FF_PS_CONSTS (renamed from NINE_STATE_FF_PSSTAGES). Signed-off-by: Axel Davy <[email protected]>
* st/nine: Add dummy ff shader stateAxel Davy2018-09-252-8/+12
| | | | | | | | | | | | | | | | | | Some states only affect the ff shader, not its constants. Currently we don't check anything and always recompute the ff shader key. However we do check for NINE_STATE_FF_OTHER and if set we reupload some constants. Thus for those states which had NINE_STATE_FF_OTHER set but didn't need it, replace by a dummy ff shader state (which is easier to understand for an external reader than just setting 0 and more future proof). Signed-off-by: Axel Davy <[email protected]>
* st/nine: Mark pointsize states as ff statesAxel Davy2018-09-251-3/+3
| | | | | | | | | | The pointsize states were missing the ff NINE_STATE_FF_OTHER flag, and thus might miss state updates when using ff. Fixes some wine tests. Signed-off-by: Axel Davy <[email protected]>
* st/nine: Minor refactor of a few NINE_STATE_* flagsAxel Davy2018-09-253-17/+14
| | | | | | | | | | | | Rename NINE_STATE_FOG_SHADER, NINE_STATE_POINTSIZE_SHADER and NINE_STATE_PS1X_SHADER into NINE_STATE_VS_PARAMS_MISC and NINE_STATE_PS_PARAMS_MISC. The behaviour is unchanged, except one minor change: D3DRS_FOGTABLEMODE doesn't need to affect VS. Signed-off-by: Axel Davy <[email protected]>
* st/nine: Increase maximum number of temp registersAxel Davy2018-09-251-1/+1
| | | | | | | | | With some test app I hit the limit. As we allocate on demand (up to the maximum), it is free to increase the limit. Signed-off-by: Axel Davy <[email protected]> CC: <[email protected]>
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