summaryrefslogtreecommitdiffstats
path: root/src
Commit message (Collapse)AuthorAgeFilesLines
* compiler: Add color system valueConnor Abbott2019-07-084-0/+18
| | | | | | | | This is nice to have with radeonsi, where color varyings are handled specially to avoid recompiles. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* radv: Use NIR barycentric intrinsicsConnor Abbott2019-07-083-191/+156
| | | | | | | | | We have to add a few lowering to deal with things that used to be dealt with inline when creating inputs. We also move the code that fills out the radv_shader_variant_info struct for linking purposes to radv_shader.c, as it's no longer tied to the NIR->LLVM lowering. Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* ac/nir: Implement barycentric intrinsicsConnor Abbott2019-07-081-0/+198
| | | | | Reviewed-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* intel/nir: Extract add_const_offset_to_baseConnor Abbott2019-07-083-74/+100
| | | | | | | | Pretty much every driver using nir_lower_io_to_temporaries followed by nir_lower_io is going to want this. In particular, radv and radeonsi in the next commits. Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* nir/lower_io_to_temporaries: Handle interpolation intrinsicsConnor Abbott2019-07-081-0/+166
| | | | | | | These weren't properly supported. This does pretty much the same thing that the radv code did. Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* nir: Avoid coalescing vars created by lower_io_to_temporariesConnor Abbott2019-07-083-0/+20
| | | | | | | | | | | | | | | Right now nir_copy_prop_vars is effectively undoing nir_lower_io_to_temporaries for inputs by propagating the original variable through the copy created in lower_io_to_temporaries. A theoretical variable coalescing pass would have the same issue with output variables, although that doesn't exist yet. To fix this, add a new bit to nir_variable, and disable copy propagation when it's set. This doesn't seem to affect any drivers now, probably since since no one uses lower_io_to_temporaries for inputs as well as copy_prop_vars, but it will fix radv once we flip on lower_io_to_temporaries for fs inputs. Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* nir: Return correct size in nir_assign_io_var_locations()Connor Abbott2019-07-081-2/+4
| | | | | | | | It was double-counting cases where multiple variables were assigned to the same slot, and not handling the case where the last variable is a compact variable. Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* nir: Handle compact variables when assigning i/o locationsConnor Abbott2019-07-081-2/+22
| | | | | | | These are used in Vulkan for clip/cull distances, instead of the GLSL lowering when the clip/cull arrays are shared. Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* nir: Move st_nir_assign_var_locations() to common codeConnor Abbott2019-07-083-115/+119
| | | | | | | | It isn't really doing anything Gallium-specific, and it's needed for handling component packing, overlapping, etc. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* radv: Make FragCoord a sysvalConnor Abbott2019-07-086-23/+14
| | | | | | | | | | load_fragcoord is already handled in common code for radeonsi, so we don't need to do anything to handle it. However, there were some passes creating NIR with the varying, so we switch them over to the sysval. In the case of nir_lower_input_attachments which is used by both radv and anv, we add handling for both until intel switches to using a sysval. Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* spirv: Add an option for making FragCoord a sysvalConnor Abbott2019-07-082-1/+11
| | | | | | | | | | On AMD, FragCoord should be a sysval because it is handled separately from all the other inputs. We were already doing this in radeonsi, but we weren't doing it with radv. It'll be much more annoying to handle VARYING_SLOT_POS in fragment shaders when we let NIR lower FS inputs for us, so here we add an option so that radv can get it as a system value. Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: Lower input attachments in NIR.Daniel Schürmann2019-07-086-36/+10
| | | | | | | | v2 (Connor) - Fix warning in release mode using MAYBE_UNUSED Reviewed-by: Connor Abbott <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: Implement nir_intrinsic_load_layer_id().Daniel Schürmann2019-07-083-1/+9
| | | | | | Reviewed-by: Connor Abbott <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* anv,nir: Move lower_input_attachments pass from ANV to NIR.Daniel Schürmann2019-07-088-12/+18
| | | | | Reviewed-by: Connor Abbott <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv/gfx10: don't emit PFP packets on ME.Dave Airlie2019-07-081-2/+3
| | | | | | | | | | | This was done for all previous GPUs. This fixes Talos Principle launch hangs. Fixes: 7e43022e8c8 (radv/gfx10: add gfx10_cs_emit_cache_flush) Reviewed-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* ac: select the GFX ring when halting waves with UMR on GFX10Samuel Pitoiset2019-07-084-6/+11
| | | | | | | | GFX10 has two rings, so UMR want to know which one to halt. Select the first one by default. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv/gfx10: Move NGG output handling outside of giant if-statement.Bas Nieuwenhuizen2019-07-081-2/+10
| | | | | | | | | | | | In merged shaders we put a big if around each shader, so both stages can have a different number of threads. However, the NGG output code still needs to run if the first shader is not executed. This can happen when there are more gs threads than vs/es threads, or when there are 0 es/vs threads (why? no clue). Fixes: ee21bd7440c "radv/gfx10: implement NGG support (VS only)" Reviewed-by: Dave Airlie <[email protected]>
* radv: Actually use VK formats for the format table.Bas Nieuwenhuizen2019-07-071-48/+20
| | | | | | | | No ETC2 or ASTC on navi so nothing to add. Fixes: 3dc5ec5d167 "radv/gfx10: generate gfx10_format_table.h" Reviewed-by: Samuel Pitoiset <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* anv: fix VkExternalBufferProperties for host allocationChia-I Wu2019-07-071-0/+10
| | | | | | | | | It was reported as unsupported previously. It should be importable and is compatible with itself. Signed-off-by: Chia-I Wu <[email protected]> Fixes: 69cc6272fbc199 ("anv: Implement VK_EXT_external_memory_host") Reviewed-by: Lionel Landwerlin <[email protected]>
* anv: fix VkExternalBufferProperties for unsupported handlesChia-I Wu2019-07-071-1/+7
| | | | | | | | compatibleHandleTypes must include the queried handle type. Signed-off-by: Chia-I Wu <[email protected]> Cc: <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]>
* radv: Handle cmask being disallowed by addrlib.Bas Nieuwenhuizen2019-07-071-0/+5
| | | | | | | alignment=0 does weird things with align64. CC: <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* radv/gfx10: enable support for NAVI10, NAVI12 and NAVI14Samuel Pitoiset2019-07-071-3/+0
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv/gfx10: Use GS rectlist when needed.Bas Nieuwenhuizen2019-07-071-0/+2
| | | | Reviewed-by: Samuel Pitoiset <[email protected]>
* radv/gfx10: implement NGG support (VS only)Samuel Pitoiset2019-07-076-22/+610
| | | | | | | | | | This needs to be cleaned up a bit, and it probably contains missing stuff and/or bugs. This doesn't fix the "half of the triangles" issue. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: Combine vs and tes output keys parts.Bas Nieuwenhuizen2019-07-074-46/+48
| | | | | | That way the same deref is valid for both shader stages. Reviewed-by: Samuel Pitoiset <[email protected]>
* radv/gfx10: Use new uconfig reg index packet for GFX10+.Bas Nieuwenhuizen2019-07-074-6/+18
| | | | | | Otherwise the hardware/firmware seems to not set the registers. Reviewed-by: Samuel Pitoiset <[email protected]>
* radv/gfx10: Set MEM_ORDERED flags on shaders.Bas Nieuwenhuizen2019-07-071-0/+9
| | | | | | Scattered because depending on stage they are at offset 24/25/27/30. Reviewed-by: Samuel Pitoiset <[email protected]>
* radv/gfx10: emit GE_CNTL instead of IA_MULTI_VGT_PARAM for legacy modeSamuel Pitoiset2019-07-072-4/+44
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv/gfx10: double the number of tessellation offchip buffers per SESamuel Pitoiset2019-07-071-3/+5
| | | | | | | | Each gfx10 shader engine corresponds to two gfx9 shader engines, so scale the number of offchip buffers accordingly. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv/gfx10: require LLVM 9+Samuel Pitoiset2019-07-071-0/+6
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv/gfx10: disable geometry and tessellation shadersSamuel Pitoiset2019-07-071-2/+2
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv/gfx10: disable binningSamuel Pitoiset2019-07-071-1/+2
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv/gfx10: disable CLEAR_STATESamuel Pitoiset2019-07-072-5/+2
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv/gfx10: disable VK_EXT_transform_feedbackSamuel Pitoiset2019-07-071-1/+1
| | | | | | | It requires a bunch of work, so disable for now. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv/gfx10: set user data base registersSamuel Pitoiset2019-07-071-17/+26
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv/gfx10: add gfx10_cs_emit_cache_flushSamuel Pitoiset2019-07-071-1/+174
| | | | | | | | The cache flush logic on GFX10 is quite different and it's implemented with a new function. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv/gfx10: set the DCC constant encoding flagSamuel Pitoiset2019-07-071-1/+2
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv/gfx10: do not declare streamout SGPRSSamuel Pitoiset2019-07-071-0/+3
| | | | | | | Streamout is completely different on GFX10. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv/gfx10: do not set stream output shader configSamuel Pitoiset2019-07-071-7/+7
| | | | | | | Transform feedback is really different on GFX10. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv/gfx10: emit VGT_VERTEX_REUSE_BLOCK_CNTL during gfx initializationSamuel Pitoiset2019-07-072-1/+3
| | | | | | | The value doesn't need to be updated for tess. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv/gfx10: update shader-related fields in si_emit_graphics()Samuel Pitoiset2019-07-071-0/+13
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv/gfx10: implement si_emit_compute()Samuel Pitoiset2019-07-071-1/+5
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv/gfx10: mask DCC tile swizzle by alignmentSamuel Pitoiset2019-07-071-1/+4
| | | | | | | | | DCC alignment can be less than the alignment of the main surface. In that case, the DCC tile swizzle needs to be masked accordingly. Should have no impact on pre-gfx10. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv/gfx10: initialize GE_{MAX,MIN}_VTX_INDX/INDX_OFFSETSamuel Pitoiset2019-07-071-1/+5
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv/gfx10: implement radv_flush_vertex_descriptors() changeSamuel Pitoiset2019-07-071-3/+10
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv/gfx10: implement fill_geom_tess_rings()Samuel Pitoiset2019-07-071-20/+57
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv/gfx10: implement radv_CmdBindDescriptorSets()Samuel Pitoiset2019-07-071-3/+11
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv/gfx10: implement write_buffer_descriptor()Samuel Pitoiset2019-07-071-3/+10
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv/gfx10: use the correct register for image descriptor dumpingSamuel Pitoiset2019-07-071-2/+5
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv/gfx10: implement radv_pipeline_generate_hw_hs()Samuel Pitoiset2019-07-071-5/+18
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-24 12:40:14 +0000