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* panfrost/midgard: Remove assemblerAlyssa Rosenzweig2019-04-241-643/+0
| | | | | | | This code is outdated and unused; now that the compiler is mature, there's no point keeping it around in-tree (or at all). Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost: Adds Bifrost shader disassembler utilityRyan Houdek2019-04-245-0/+2434
| | | | | | | | | | | | | This code is stable and can live upstream independently while the rest of the Bifrost stack comes up. v2: Added a verbose flag to hide away some of the more verbose features that nobody really needs [The Bifrost disassembler is written by Connor Abbott, Lyude Paul, and Ryan Houdek.] Reviewed-by: Alyssa Rosenzweig <[email protected]>
* panfrost/midgard: Add "op commutes?" propertyAlyssa Rosenzweig2019-04-242-49/+36
| | | | Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost/midgard: Refactor opcode tablesAlyssa Rosenzweig2019-04-244-227/+124
| | | | | | | | | | | We create an all-encompassing opcode table for handling name and properties, removing a number of ad hoc opcode tables which became brittle and quickly out of date. While we're at it, we fix some incorrect opcodes relating to ball/bany, and move a small function out to midgard_compile.c. Together these changes should allow compilation without warnings, along with helping the codebase health considerably. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost/midgard: Optimize MIR in progress loopAlyssa Rosenzweig2019-04-241-5/+11
| | | | Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost/midgard: Implement copy propagationAlyssa Rosenzweig2019-04-242-1/+78
| | | | | | | | | Most copy prop should occur at the NIR level, but we generate a fair number of moves implicitly ourselves, etc... long story short, it's a net win to also do simple copy prop + DCE on the MIR. As a bonus, this fixes the weird imov precision bug once and for good, I think. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost/midgard: Set integer modsAlyssa Rosenzweig2019-04-241-10/+28
| | | | Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost/midgard: Document sign-extension/zero-extension bits (vector)Alyssa Rosenzweig2019-04-243-18/+57
| | | | | | | | For floating point ops, these bits determine the "negate?" and "abs?" modifiers. For integer ops, it turns out they control how sign/zero extension work, useful for mixing types. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost/midgard: Update integer op listAlyssa Rosenzweig2019-04-241-10/+21
| | | | | | | In the future, we might want to switch to a table-based approach, but for now, at least have it current. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost/midgard: Remove unused mir_next_blockAlyssa Rosenzweig2019-04-241-7/+0
| | | | Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost/midgard: Fix off-by-one in successor analysisAlyssa Rosenzweig2019-04-241-2/+4
| | | | | | | This reduces register pressure substantially since we get smaller liveness ranges. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost/midgard: Track loop depthAlyssa Rosenzweig2019-04-241-7/+10
| | | | | | This fixes nested loops. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost/midgard: Dead code eliminate MIRAlyssa Rosenzweig2019-04-241-15/+10
| | | | | | | | We reshuffle the existing "dead move elimination" pass into a generic dead code elimination layer, fixing bugs incurred with looping in the process. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost: Use actual imov instructionAlyssa Rosenzweig2019-04-241-1/+1
| | | | | | | The bug this worked around is no longer applicable, it seems -- remove the hack that breaks more than it fixes. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost: Disable indirect outputs for nowAlyssa Rosenzweig2019-04-242-3/+8
| | | | | | | The hardware needs this lowered anyway; for now, might as well use mesa's default lowering for pure conformance reasons. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost/midgard: imul can only run on *mulAlyssa Rosenzweig2019-04-241-1/+1
| | | | | | | | This restriction makes sense logically. Not sure why it wasn't obeyed before. In conjunction with previous commit's disclaimer, fixes dEQP-GLES2.functional.shaders.loop.for_dynamic_iterations.* Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost/midgard: Don't try to inline constants on branchesAlyssa Rosenzweig2019-04-241-0/+3
| | | | | | | | Along with a corresponding fix to the move elimination pass (not included here yet -- I just have it disabled for now), this will fix dEQP-GLES2.functional.shaders.loops.for_uniform_iterations.* Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost: Respect backwards branches in RAAlyssa Rosenzweig2019-04-241-14/+69
| | | | | | | Fixes a bunch of issues with looping. Honestly, I'm not sure why loops worked at all before. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost/midgard: Remove useless MIR dumpAlyssa Rosenzweig2019-04-241-2/+0
| | | | Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost/midgard: Respect component of bcsel conditionAlyssa Rosenzweig2019-04-241-7/+22
| | | | | | Fixes a bunch of non-vec4 indexing.varying_array tests. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost/midgard: Implement indirect loads of varyings/UBOsAlyssa Rosenzweig2019-04-242-16/+76
| | | | | | | | This adds preliminary support for indirect loads of varying arrays and uniform arrays, bringing a few new tests in shader.indexing.* to passing, although there remains a number of cases still missing. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost/midgard: Pipe through varying arraysAlyssa Rosenzweig2019-04-241-1/+5
| | | | | | | | Varying arrays sometimes are lowered to a series of directly accessed varyings (which we handled okay), but when indirectly accessed, they appear as a single array; we need to handle this as well. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost/mdg/disasm: Print raw varying_parametersAlyssa Rosenzweig2019-04-241-1/+1
| | | | | | | | | | The semantics of this field are not well understood; it is better to print it unconditionally along with the other unknown state, rather than silently eat the value. Without this change, some critical state was being lost in some shaders (notably, the offset for load/store scratchpad intructions found in shaders that spill registers.) Signed-off-by: Alyssa Rosenzweig <[email protected]>
* iris: Prefer staging blits when destination supports CCS_E.Kenneth Graunke2019-04-231-1/+1
| | | | | | | | | | Otherwise our textures don't get color compression. Thanks to Eero Tamminen for noticing this was missing! Improves performance of GLB27_FillTestC24Z16 on my Apollolake laptop with single channel RAM by 2.3x. Reported-by: Eero Tamminen <[email protected]>
* gallium: replace drm_driver_descriptor::configuration with driconf_xmlMarek Olšák2019-04-2315-210/+45
| | | | | | PIPE_CAPs are better. Reviewed-by: Kenneth Graunke <[email protected]>
* gallium: replace DRM_CONF_SHARE_FD with PIPE_CAP_DMABUFMarek Olšák2019-04-2314-97/+12
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* gallium: replace DRM_CONF_THROTTLE with PIPE_CAP_MAX_FRAMES_IN_FLIGHTMarek Olšák2019-04-2323-72/+37
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* st/dri: simplify throttling codeMarek Olšák2019-04-233-6/+3
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* gallium: document conservative rasterization flagsMarek Olšák2019-04-232-0/+16
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* intel/compiler: Lower ffma on Gen4 and Gen5Ian Romanick2019-04-231-0/+4
| | | | | | | | | | | flrp32 is also a 3-source instruction, but there is another pending series that handles that for Gen4 and Gen5. v2: Rebase on "intel/compiler: Don't have sepearate, per-Gen nir_options" Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* intel/compiler: Don't have sepearate, per-Gen nir_optionsIan Romanick2019-04-231-31/+11
| | | | | | | | | Instead, just have separate scalar vs. vector nir_options and do per-Gen "fix ups". Suggested-by: Jason Ekstrand <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* glsl: Silence may unused parameter warnings in glsl/ir.hIan Romanick2019-04-231-1/+1
| | | | | | | | | | | | | Every file that included glsl/ir.h had a warning like: src/compiler/glsl/ir.h: In member function ‘virtual bool ir_rvalue::is_lvalue(const _mesa_glsl_parse_state*) const’: src/compiler/glsl/ir.h:236:64: warning: unused parameter ‘state’ [-Wunused-parameter] virtual bool is_lvalue(const struct _mesa_glsl_parse_state *state = NULL) const ^ Cc: Samuel Pitoiset <[email protected]> Fixes: fa4ebf6b8d9 ("glsl: add _mesa_glsl_parse_state object to is_lvalue()") Reviewed-by: Sagar Ghuge <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* st/mesa/radeonsi: fix race between destruction of types and shader compilationTimothy Arceri2019-04-2411-17/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | Commit 624789e3708c moved the destruction of types out of atexit() and made use of a ref count instead. This is useful for avoiding a crash where drivers such as radeonsi are still compiling in a thread when the app exits and has not called MakeCurrent to change from the current context. While the above scenario is technically an app bug we shouldn't crash. However that change caused another race condition between the shader compilation tread in radeonsi and context teardown functions. This patch makes two changes to fix this new problem: First we explicitly call _mesa_destroy_shader_compiler_types() when destroying the st context rather than calling it indirectly via _mesa_free_context_data(). We do this as we must call it after st_destroy_context_priv() so that we don't destory the glsl types before the compilation threads finish. Next wait for the shader threads to finish in si_destroy_context() this also means we need to call context destroy before destroying the queues in si_destroy_screen(). Fixes: 624789e3708c ("compiler/glsl: handle case where we have multiple users for types") Reviewed-by: Marek Olšák <[email protected]>
* radv: Add adaptive_sync driconfig option and enable it by default.Bas Nieuwenhuizen2019-04-231-0/+3
| | | | Reviewed-by: Samuel Pitoiset <[email protected]>
* vulkan/wsi: Add X11 adaptive sync support based on dri options.Bas Nieuwenhuizen2019-04-237-5/+57
| | | | | | | | | | | | | | | | | | | | | | | | The dri options are optional. When the dri options are not provided the WSI will not use adaptive sync. FWIW I think for xf86-video-amdgpu this still requires an X11 config option, so only people who opt in can get possible regressions from this. So then the remaining question is: why do this in the WSI? It has been suggested in another MR that the application sets this. However, I disagree with that as I don't think we'll ever get a reasonable set of applications setting it. The next questions is whether this can be a layer. It definitely can be as implemented now. However, I think this generally fits well with the function of the WSI. Furthemore, for e.g. the DISPLAY WSI this is much harder to do in a layer. Of course, most of the WSI could almost be a layer, but I think this still fits best in the WSI. Acked-by: Jason Ekstrand <[email protected]>
* radv: Add support for driconf.Bas Nieuwenhuizen2019-04-233-3/+23
| | | | | | | | | This includes 0 options. The cache parsing is located at a position where we can easily add config filtering by VkApplicationInfo. Reviewed-by: Samuel Pitoiset <[email protected]>
* iris: add support for INTEL_conservative_rasterizationMike Blumenkrantz2019-04-232-11/+34
| | | | | | | | | this hooks up the iris gallium driver to existing mesa bits which handle the implementation resolves kwg/mesa#8 Reviewed-by: Kenneth Graunke <[email protected]>
* st/mesa: indicate intel extension support for inner_coverage based on capMike Blumenkrantz2019-04-233-0/+4
| | | | | | | | if the driver (iris) indicates support for the inner_coverage pipe cap, this will set the necessary states in the driver flags and rasterizer structs Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* gallium: add pipe cap for inner_coverage conservative raster modeMike Blumenkrantz2019-04-233-0/+4
| | | | | | | this can be used by drivers which support the extension to indicate support Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* iris: Fix DrawTransformFeedback math when there's a buffer offsetKenneth Graunke2019-04-233-0/+14
| | | | | | | We need to subtract the starting offset from the final offset before dividing by the stride. See src/intel/vulkan/genX_cmd_buffer.c:3142. Not known to fix anything.
* iris: Make some offset math helpers take a const isl_surf pointerKenneth Graunke2019-04-231-2/+2
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* spirv: Handle SpvOpDecorateIdCaio Marcelo de Oliveira Filho2019-04-231-0/+4
| | | | | | | | | | | This operation decorate with an Id instead of a Literal or String. It is used by HlslCounterBufferGOOGLE (provided by SPV_GOOGLE_hlsl_functionality1). Even if we don't do anything with that decoration, we must be able to parse SPIR-V that uses it. Fixes: 891886da2f9 "spirv: Add no-op support for VK_GOOGLE_hlsl_functionality1" Reviewed-by: Jason Ekstrand <[email protected]>
* spirv: Rename vtn_decoration literals to operandsCaio Marcelo de Oliveira Filho2019-04-235-39/+39
| | | | | | | | Decorations (and ExecutionModes) can have not only literals, but also Ids associated with them. So rename the field to the more general name "Operand" used by the spec. Reviewed-by: Jason Ekstrand <[email protected]>
* anv: fix argument name for vkCmdEndQueryLionel Landwerlin2019-04-241-2/+2
| | | | | | | | | | Doesn't fix anything but it's not the right function prototype. Signed-off-by: Lionel Landwerlin <[email protected]> Fixes: 673f33c77dd765 ("anv: Implement CmdBegin/EndQueryIndexed") Reviewed-by: Caio Marcelo de Oliveira Filho <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Sagar Ghuge <[email protected]>
* virgl: skip empty cmdbufsChia-I Wu2019-04-232-0/+9
| | | | | | | | Several empty cmdbufs are submitted by app/xserver per frame, from glamor_block_handler for example. Let's skip them. Signed-off-by: Chia-I Wu <[email protected]> Reviewed-by: Gurchetan Singh <[email protected]>
* gallium: Remove the malloc pipebuffer manager.Eric Anholt2019-04-234-209/+0
| | | | | | | | This has been unused since r600 stopped using it in 2010. Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Jose Fonseca <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]>
* gallium: Remove the "alt" pipebuffer manager interface.Eric Anholt2019-04-234-127/+0
| | | | | | | | | This one would allocate from two underlying pools, but has never been used. Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Jose Fonseca <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]>
* gallium: Remove the ondemand pipebuffer manager.Eric Anholt2019-04-234-322/+0
| | | | | | | | I couldn't find any uses in the tree since its introduction. Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Jose Fonseca <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]>
* gallium: Remove the pool pipebuffer manager.Eric Anholt2019-04-234-342/+1
| | | | | | | | | Noticed while trying to decide if pipebuffer was of any use to me, and found that nothing has used it in the last 10 years at least. Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Jose Fonseca <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]>
* freedreno: a2xx: same gmem2mem sequence for all tilesJonathan Marek2019-04-231-12/+25
| | | | | | | | | | Set REG_A2XX_RB_COPY_DEST_OFFSET in the tile init as it won't get touched by the draw batch. Then gmem2mem is the same for all tiles. Similar to what is done in a6xx, but only for gmem2mem. Signed-off-by: Jonathan Marek <[email protected]> Reviewed-by: Rob Clark <[email protected]>
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