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* freedreno/ir3: implement fdd{x,y}_coarse opcodesJonathan Marek2019-10-141-0/+2
| | | | | | | Same as regular fddx/fddy. Signed-off-by: Jonathan Marek <jonathan@marek.ca> Reviewed-by: Rob Clark <robclark@gmail.com>
* freedreno/ir3: increase size of inputs/outputs arraysJonathan Marek2019-10-141-2/+2
| | | | | | | Makes it possible to support 32 varyings. Signed-off-by: Jonathan Marek <jonathan@marek.ca> Reviewed-by: Rob Clark <robclark@gmail.com>
* freedreno/ir3: remove input ncomp fieldJonathan Marek2019-10-144-6/+2
| | | | | Signed-off-by: Jonathan Marek <jonathan@marek.ca> Reviewed-by: Rob Clark <robclark@gmail.com>
* etnaviv: fix vertex buffer state emission for single stream GPUsLucas Stach2019-10-141-1/+1
| | | | | | | | | GPUs with a single supported vertex stream must use the single state address to program the stream. Fixes: 3d09bb390a39 (etnaviv: GC7000: State changes for HALTI3..5) Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Reviewed-by: Jonathan Marek <jonathan@marek.ca>
* gallivm/draw/swr: make the gs_iface not depend on tgsi.Dave Airlie2019-10-154-80/+83
| | | | | | | | | | | | | This gs_iface doesn't seem to require a dependence on the tgsi context, except for the swr end prim code. This refactors the API to include all the info that the swr code needs in the interface rather than having to dig it out of the struct inheritance. This is a precursor to adding NIR support to llvmpipe. Reviewed-by: Jan Zielinski <jan.zielinski@intel.com>
* iris: Implement the Gen < 9 tessellation quads workaroundKenneth Graunke2019-10-141-0/+3
| | | | | | | | Fixes several CTS tests: - KHR-GL46.tessellation_shader.vertex.vertex_spacing - KHR-GL46.tessellation_shader.tessellation_shader_point_mode.points_verification Fixes: 823609b1a39 ("iris/WIP: add broadwell support")
* anv: Advertise VK_KHR_spirv_1_4Caio Marcelo de Oliveira Filho2019-10-141-0/+1
| | | | Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
* vulkan: Update the XML and headers to 1.1.125Caio Marcelo de Oliveira Filho2019-10-141-5/+11
| | | | Acked-by: Jason Ekstrand <jason@jlekstrand.net>
* android: amd/common: export amd/llvm headersMauro Rossi2019-10-141-0/+1
| | | | | | | | | | | | | Fixes the following building error: external/mesa/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c:42:10: fatal error: 'ac_llvm_util.h' file not found ^~~~~~~~~~~~~~~~ 1 error generated. Fixes: 3a08110 ("amd: Move all amd/common code that depends on LLVM to amd/llvm.") Signed-off-by: Mauro Rossi <issor.oruam@gmail.com> Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
* gallium: rename PIPE_CAP_MAX_FRAMES_IN_FLIGHT to PIPE_CAP_THROTTLEJames Xiong2019-10-147-9/+7
| | | | | | | | | v2: [ Michel Dänzer ] * Update src/gallium/docs/source/screen.rst accordingly Signed-off-by: James Xiong <james.xiong@intel.com> Reviewed-by: Michel Dänzer <mdaenzer@redhat.com> # v1 Reviewed-by: Marek Olšák <marek.olsak@amd.com> # v1
* gallium: simplify throttle implementationJames Xiong2019-10-144-110/+13
| | | | | | | | | | | All gallium drivers currently set MAX_FRAME_IN_FLIGHT to either 1 or 0, which means that the drivers either throttle on the previous render or don't throttle, the current implementation is more complicated than necessary and can be simplified. Signed-off-by: James Xiong <james.xiong@intel.com> Reviewed-by: Michel Dänzer <mdaenzer@redhat.com> Reviewed-by: Marek Olšák <marek.olsak@amd.com>
* radv: fix DCC fast clear code for intensity formatsSamuel Pitoiset2019-10-143-9/+31
| | | | | | | | | | This fixes a rendering issue with DiRT 4 on GFX10. Only GFX10 was affected because intensity formats are different. Cc: 19.2 <mesa-stable@lists.freedesktop.org> Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/1923 Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
* gbm: use size_t for array indexesEric Engestrom2019-10-131-10/+5
| | | | | Signed-off-by: Eric Engestrom <eric@engestrom.ch> Reviewed-by: Eric Anholt <eric@anholt.net>
* gbm: replace NULL sentinel with explicit ARRAY_SIZE()Eric Engestrom2019-10-131-9/+12
| | | | | Signed-off-by: Eric Engestrom <eric@engestrom.ch> Reviewed-by: Eric Anholt <eric@anholt.net>
* gbm: replace 1/0 bool with true/falseEric Engestrom2019-10-131-8/+8
| | | | | Signed-off-by: Eric Engestrom <eric@engestrom.ch> Reviewed-by: Eric Anholt <eric@anholt.net>
* gbm: turn 0/-1 bool into true/falseEric Engestrom2019-10-131-6/+7
| | | | | Signed-off-by: Eric Engestrom <eric@engestrom.ch> Reviewed-by: Eric Anholt <eric@anholt.net>
* radv: add exported symbols checkEric Engestrom2019-10-131-0/+13
| | | | | | | Signed-off-by: Eric Engestrom <eric.engestrom@intel.com> Reviewed-by: Dylan Baker <dylan@pnwbakers.com> Reviewed-by: Emil Velikov <emil.velikov@collabora.com> Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
* anv: add exported symbols checkEric Engestrom2019-10-131-0/+13
| | | | | | | Signed-off-by: Eric Engestrom <eric.engestrom@intel.com> Reviewed-by: Dylan Baker <dylan@pnwbakers.com> Reviewed-by: Emil Velikov <emil.velikov@collabora.com> Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
* panfrost: Fix support for packed 24-bit formatsBoris Brezillon2019-10-131-1/+1
| | | | | | | | | pan_pack_color() color was missing the 24-bit packed format case. Looks like putting the clear color in a 32-bit slot does the trick. Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
* glsl: fix crash compiling bindless samplers inside unnamed UBOsTimothy Arceri2019-10-121-5/+5
| | | | | | | | | | The check to see if we were dealing with a buffer block was too late and only worked for named UBOs. Fixes: f32b01ca435c "glsl/linker: remove ubo explicit binding handling" Reviewed-by: Marek Olšák <marek.olsak@amd.com> Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/1900
* glsl/builtin: Add alternate versions of atan using new opsNeil Roberts2019-10-121-2/+31
| | | | | | | | | | Adds alternate versions of the atan builtin functions that use ir_unop_atan and ir_binop_atan2 instead of inlining to the IR implementation of the function. These alternatives are selected if the IR is going to be consumed by NIR. In that case the IR ops will be translated to the appropriate NIR op. Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
* glsl: Add opcodes for atan and atan2Neil Roberts2019-10-126-0/+31
| | | | | | | | Adds ir_binop_atan2 and ir_unop_atan. When converting to NIR these are expanded out using the appropriate builtin generator. If they are used with anything else then it will just hit an assert. Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
* nir/builtin: Add extern "C" guards to nir_builtin_builder.hNeil Roberts2019-10-121-0/+8
| | | | | | That way it can also be included from a C++ source. Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
* nir/builtin: Add #include u_math.h to the headerNeil Roberts2019-10-121-0/+1
| | | | | | | The inline functions use M_PI so they should include a header to make sure it is defined. Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
* nir/builder: Move nir_atan and nir_atan2 from SPIR-V translatorNeil Roberts2019-10-123-153/+156
| | | | | | | Moves build_atan and build_atan2 into nir_builtin_builder. The goal is to be able to use this from the GLSL translator too. Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
* egl: Configs w/o double buffering support have no `EGL_WINDOW_BIT`.Hal Gentz2019-10-1110-7/+78
| | | | | | | | | | | | | | | | When users pass a config to `eglCreateWindowSurface` it requests double buffering, but if the config doesn't have the appropriate `__DRIconfig`, `eglCreateWindowSurface` fails with a `EGL_BAD_MATCH`. Given that such behaviour is completely unacceptable, we drop the `EGL_WINDOW_BIT` if we don't have at least one `__DRIconfig` supporting double buffering, otherwise dropping the `EGL_PIXMAP_BIT`. Fixes: 049f343e8ac "egl: Allow 24-bit visuals for 32-bit RGBA8888 configs" Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=67676 Cc: mesa-stable@lists.freedesktop.org Reviewed-by: Adam Jackson <ajax@redhat.com> Signed-off-by: Hal Gentz <zegentzy@protonmail.com>
* egl: Puts RGBA visuals in the second config selection group.Hal Gentz2019-10-111-1/+9
| | | | | | | | | | | | | | | That way applications don't get windows that are compositor alpha-blended accidentally. In the ideal world, this would be done by the xserver, as it does for GLX, however, an appropriate place could not be found, so it's being placed here instead. Fixes: 049f343e8ac "egl: Allow 24-bit visuals for 32-bit RGBA8888 configs" Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=67676 Cc: mesa-stable@lists.freedesktop.org Reviewed-by: Adam Jackson <ajax@redhat.com> Signed-off-by: Hal Gentz <zegentzy@protonmail.com>
* egl: Fixes transparency with EGL and X11.Hal Gentz2019-10-117-17/+35
| | | | | | | | | | | | | This commit does this by allowing both RGB and RGBA visuals to match with EGL configs. We also expose the `EGL_MESA_config_select_group` egl extension, which is similar to GLX's visual select group extension, to allow the RGBA visuals to get less priority. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=67676 Fixes: 049f343e8ac "egl: Allow 24-bit visuals for 32-bit RGBA8888 configs" Cc: mesa-stable@lists.freedesktop.org Reviewed-by: Adam Jackson <ajax@redhat.com> Signed-off-by: Hal Gentz <zegentzy@protonmail.com>
* intel/fs/gen12: Use TCS 8_PATCH mode.Kenneth Graunke2019-10-112-6/+8
| | | | Reviewed-by: Francisco Jerez <currojerez@riseup.net>
* intel/fs/gen12: Implement gl_FrontFacing on gen12+.Jason Ekstrand2019-10-112-2/+25
| | | | | | | | The bit moved on gen12 in order to prepare for dual-SIMD8 dispatch. This implementation isn't an entirely complete as it only works on SIMD8 and SIMD16 and not dual-SIMD8. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
* intel/fs/gen11+: Fix CS_OPCODE_CS_TERMINATE codegen.Francisco Jerez2019-10-112-8/+11
| | | | | | | | | | | | | Apparently the ts_request_type and ts_resource_select thread spawner message descriptor bits were removed from the hardware at least since ICL. Drop them in order to avoid assertion failures on Gen12+ platforms which don't have any encoding for this. On Gen9+ these are probably just ignored by the hardware, so this is unlikely to have had any functional implications prior to Gen12. v2: Mark TS message fields as non-existing in brw_inst.h on ICL. (Caio) Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
* intel/fs/gen12: Fix barrier codegen.Francisco Jerez2019-10-112-2/+7
| | | | | | | | The WAIT instruction has been removed, but SYNC.bar can be used instead to wait for a notification on n0.0. Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
* intel/eu: Don't set notify descriptor field of gateway barrier message.Francisco Jerez2019-10-111-1/+0
| | | | | | | | | | Apparently this field was removed on SKL, and according to the hardware docs for previous platforms "This field is only valid for a ForwardMsg message. It is ignored for other messages. The BarrierMsg message always increments the N0 notification counter". Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
* intel/ir/gen12: Update assert in brw_stage_has_packed_dispatch().Francisco Jerez2019-10-111-1/+1
| | | | | | | Confirmed no regressions after a full Piglit run on TGL with the brw_fs_test_dispatch_packing() test enabled. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
* intel/eu/validate/gen12: Don't blow up on indirect src0.Jason Ekstrand2019-10-111-1/+2
| | | | | | | They look like a NULL source if you don't look at the address mode. Reviewed-by: Francisco Jerez <currojerez@riseup.net> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
* intel/eu/validate/gen12: Validation fixes for SEND instruction.Francisco Jerez2019-10-111-22/+28
| | | | | | | | The following fix-up by Jordan Justen is squashed in: intel/eu/validate: gen12 send instruction doesn't have a dst type field Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
* intel/eu/validate/gen12: Fix validation of SYNC instruction.Francisco Jerez2019-10-111-1/+1
| | | | | | | src0 will typically be null for this instruction. Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
* intel/eu/validate/gen12: Implement integer multiply restrictions in EU ↵Francisco Jerez2019-10-111-0/+33
| | | | | | | | validator. Due to hardware bug filed as HSDES#1604601757. Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
* intel/ir: Lower fpow on Gen12.Jordan Justen2019-10-111-0/+1
| | | | | | Signed-off-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Francisco Jerez <currojerez@riseup.net> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
* intel/fs/gen12: Don't support source mods for 32x16 integer multiply.Francisco Jerez2019-10-111-0/+18
| | | | | | | | | | Due to hardware bug filed as HSDES#1604601757. v2: Only return if result of fs_inst::can_do_source_mods() is known to be false for the case new orthogonal restrictions are implemented below in the future. (Caio) Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
* intel/disasm: Disassemble register file of split SEND sources.Francisco Jerez2019-10-111-1/+4
| | | | Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
* intel/disasm: Don't disassemble saturate control on SEND instructions.Francisco Jerez2019-10-111-2/+4
| | | | | | | The field is gone on Gen12+ and it was illegal on previous generations. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
* intel/disasm/gen12: Disassemble Gen12 SEND instructions.Francisco Jerez2019-10-111-4/+18
| | | | Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
* intel/disasm/gen12: Disassemble Gen12 SYNC instruction.Francisco Jerez2019-10-111-0/+14
| | | | | Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
* intel/disasm/gen12: Disassemble three-source instruction source and ↵Francisco Jerez2019-10-111-13/+32
| | | | | | destination regions. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
* intel/disasm/gen12: Fix disassembly of some common instruction controls.Francisco Jerez2019-10-111-4/+9
| | | | Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
* intel/disasm/gen12: Disassemble software scoreboard information.Francisco Jerez2019-10-111-0/+16
| | | | Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
* intel/fs/gen12: Demodernize software scoreboard lowering pass.Francisco Jerez2019-10-111-81/+163
| | | | | | | Kept as a separate commit in order to avoid distracting reviewers of the software scoreboard pass with memory management boilerplate. Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
* intel/fs/gen12: Introduce software scoreboard lowering pass.Francisco Jerez2019-10-115-0/+946
| | | | | | | | | | | | | | | | | | | | | | Gen12+ hardware lacks the register scoreboard logic that used to guarantee data coherency between register reads and writes in previous generations. This lowering pass runs after register allocation in order to make up for it. It works by performing global dataflow analysis in order to determine the set of potential dependencies of every instruction in the shader, and then inserts any required SWSB annotations and additional SYNC instructions in order to guarantee data coherency. v2: Drop unnecessary _safe list iteration (Caio). v3: Temporarily workaround potential WaR hazard between FPU instruction and subsequent out-of-order write, pending clarification from the hardware team. Drop redundant tracking of implicit access of acc0-1, since the hardware guarantees coherency of these (but not the other accumulators...). Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
* intel/fs/gen12: Add scheduling information to the IR.Francisco Jerez2019-10-112-0/+3
| | | | Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>