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* i965: Use UD types for gl_SampleID setupJason Ekstrand2018-01-111-3/+3
| | | | | | | | We already had to switch all of the W types to UW to prevent issues with vector immediates on gen10. We may as well use unsigned types everywhere. Reviewed-by: Matt Turner <[email protected]>
* i965/fs: Use UW types when using V immediatesJason Ekstrand2018-01-112-5/+5
| | | | | | | | | | | | | | | | | | | | | | Gen 10 has a strange hardware bug involving V immediates with W types. It appears that a mov(8) g2<1>W 0x76543210V will actually result in g2 getting the value {3, 2, 1, 0, 3, 2, 1, 0}. In particular, the bottom four nibbles are repeated instead of the top four being taken. (A mov of 0x00003210V yields the same result.) This bug does not appear in any hardware documentation as far as we can tell and the simulator does not implement the bug either. Commit 6132992cdb858268af0e985727d80e4140be389c was mostly a no-op except that it changed the type of the subgroup invocation from UW to W and caused us to tickle this bug with basically every compute shader that uses any sort of invocation ID (which is most of them). This is also potentially an issue for geometry shader input pulls and SampleID setup. The easy solution is just to change the few places where we use a vector integer immediate with a W type to use a UW type. Reviewed-by: Matt Turner <[email protected]> Cc: [email protected] Fixes: 6132992cdb858268af0e985727d80e4140be389c
* ac/nir: fix translation of nir_op_fsign for doublesTimothy Arceri2018-01-121-7/+19
| | | | | | | | Without this we end up with the llvm error message: "Both operands to a binary operator are not of the same type!" Reviewed-by: Samuel Pitoiset <[email protected]>
* ac: add f64_0 to the llvm build contextTimothy Arceri2018-01-122-0/+2
| | | | Reviewed-by: Samuel Pitoiset <[email protected]>
* ac/nir: fix translation of nir_op_frcp for doublesTimothy Arceri2018-01-121-1/+2
| | | | | | | | Without this we end up with the llvm error message: "Both operands to a binary operator are not of the same type!" Reviewed-by: Samuel Pitoiset <[email protected]>
* ac/nir: fix translation of nir_op_frsq for doublesTimothy Arceri2018-01-121-1/+2
| | | | | | | | Without this we end up with the llvm error message: "Both operands to a binary operator are not of the same type!" Reviewed-by: Samuel Pitoiset <[email protected]>
* ac: add f64_1 to the llvm build contextTimothy Arceri2018-01-122-0/+2
| | | | Reviewed-by: Samuel Pitoiset <[email protected]>
* radv: reset semaphores & fences on sync_file export.Bas Nieuwenhuizen2018-01-111-0/+16
| | | | | | | | | | | | | | | | | | Per spec: "Additionally, exporting a fence payload to a handle with copy transference has the same side effects on the source fence’s payload as executing a fence reset operation. If the fence was using a temporarily imported payload, the fence’s prior permanent payload will be restored." And similar for semaphores: "Additionally, exporting a semaphore payload to a handle with copy transference has the same side effects on the source semaphore’s payload as executing a semaphore wait operation. If the semaphore was using a temporarily imported payload, the semaphore’s prior permanent payload will be restored." Fixes: 42bc25a79c "radv: Advertise sync fd import and export." Reviewed-by: Dave Airlie <[email protected]>
* Revert "Revert "i965/fs: Use align1 mode on ternary instructions on Gen10+""Matt Turner2018-01-111-4/+8
| | | | | | This reverts commit 2d0457203871c843ebfc90fb895b65a9b14cd9bb. Acked-by: Scott D Phillips <[email protected]>
* i965/fs: Add/use functions to convert to 3src_align1 vstride/hstrideMatt Turner2018-01-111-28/+41
| | | | | | | | | | Some cases weren't handled, such as stride 4 which is needed for 64-bit operations. Presumably fixes the assertion failure mentioned in commit 2d0457203871 (Revert "i965/fs: Use align1 mode on ternary instructions on Gen10+") but who can really say since the commit neglected to list any of them! Reviewed-by: Scott D Phillips <[email protected]>
* anv: Make sure state on primary is correct after CmdExecuteCommandsAlex Smith2018-01-111-0/+9
| | | | | | | | | | | | | | | | | After executing a secondary command buffer, we need to update certain state on the primary command buffer to reflect changes by the secondary. Otherwise subsequent commands may not have the correct state set. This fixes various issues (rendering errors, GPU hangs) seen after executing secondary command buffers in some cases. v2 (Jason Ekstrand): - Reset to invalid values instead of pulling from the secondary - Change the comment to be more descriptive Signed-off-by: Alex Smith <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Cc: [email protected]
* svga: simplify failure code in emit_rss_vgpu9()Brian Paul2018-01-111-17/+12
| | | | | | | No need for a goto. Reviewed-by: Neha Bhende <[email protected]> Reviewed-by: Charmaine Lee <[email protected]>
* svga: remove unused fail parameter to EMIT_RS(), EMIT_RS_FLOAT()Brian Paul2018-01-111-57/+57
| | | | | Reviewed-by: Neha Bhende <[email protected]> Reviewed-by: Charmaine Lee <[email protected]>
* svga: add assertion in svga_queue_rs()Brian Paul2018-01-111-0/+1
| | | | | Reviewed-by: Neha Bhende <[email protected]> Reviewed-by: Charmaine Lee <[email protected]>
* svga: whitespace/formatting fixes in svga_state_rss.cBrian Paul2018-01-111-79/+75
| | | | | Reviewed-by: Neha Bhende <[email protected]> Reviewed-by: Charmaine Lee <[email protected]>
* anv: Import mako templates only during execution of anv_extensionsAndres Gomez2018-01-111-5/+5
| | | | | | | | | | | | | | | | | | anv_extensions usage from anv_icd was bringing the unwanted dependency of mako templates for the latter. We don't want that since it will force the dependency even for distributable tarballs which was not needed until now. Jason suggested this approach. v2: Patch simplification (Jason). Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104551 Fixes: 0ab04ba979b ("anv: Use python to generate ICD json files") Cc: Jason Ekstrand <[email protected]> Cc: Emil Velikov <[email protected]> Signed-off-by: Andres Gomez <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* glsl: cleanup shader_cache header guardTapani Pälli2018-01-111-3/+3
| | | | | Signed-off-by: Tapani Pälli <[email protected]> Reviewed-by: Timothy Arceri <[email protected]>
* anv: fix maxDescriptorSet* limitsSamuel Iglesias Gonsálvez2018-01-111-5/+5
| | | | | | | | | | | | | | | "The maxDescriptorSet* limit is n times the corresponding maxPerStageDescriptor* limit, where n is the number of shader stages supported by the VkPhysicalDevice. If all shader stages are supported, n = 6 (vertex, tessellation control, tessellation evaluation, geometry, fragment, compute)." Fixes: dEQP-VK.api.info.device.properties Signed-off-by: Samuel Iglesias Gonsálvez <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* ac: add load_patch_vertices_in() to the abiTimothy Arceri2018-01-113-7/+26
| | | | | | | | | | | | | Fixes the follow test for radeonsi nir: tests/spec/arb_tessellation_shader/execution/quads.shader_test Also stops 8 other tests from crashing, they now just fail e.g. tcs-output-array-float-index-rd-after-barrier.shader_test Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]>
* ac/nir: Sanitize location_frac for local variables.Bas Nieuwenhuizen2018-01-111-0/+1
| | | | | | | | If they were promoted from inputs/outputs, they could have a non-zero value left over, which messed with our store handling. Fixes: 06f05040eb "radv: Link shaders." Reviewed-by: Timothy Arceri <[email protected]>
* tgsi: include struct definitions for tgsi_build declarationsRob Herring2018-01-101-5/+1
| | | | | | | | | | | | | | Many of the functions declared in tgsi_build.h return structs (not struct pointers). Therefore the full struct definitions are needed to avoid warnings or errors: In file included from src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp:23: external/mesa3d/src/gallium/auxiliary/tgsi/tgsi_build.h:47:1: error: 'tgsi_build_header' has C-linkage specified, but returns incomplete type 'struct tgsi_header' which could be incompatible with C [-Werror,-Wreturn-type-c-linkage] This error shows up on Android builds using clang and -Werror. Cc: Ilia Mirkin <[email protected]> Signed-off-by: Rob Herring <[email protected]>
* swr: Handle indirect indices in GSGeorge Kyriazis2018-01-101-8/+39
| | | | | | | | | | | | | | | BuilderSWR::swr_gs_llvm_fetch_input() (and consequently swr_gs_llvm_fetch_input()), did not handle the case where is_vindex_indirect or is_aindex_direct is set. Implement it, using the code in draw_llvm.c as a guideline. Fixes the following piglit tests: dynamic_input_array_index (crash) gs-input-array-vec4-index-rd vs-output-array-vec4-index-wr-before-gs Reviewed-by: Bruce Cherniak <[email protected]>
* amd/common: use ac_build_buffer_load() for emitting UBO loadsSamuel Pitoiset2018-01-101-14/+3
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* amd/common: import get_{load,store}_intr_attribs() from RadeonSISamuel Pitoiset2018-01-103-31/+25
| | | | | | | v2: move those helpers to the header and use static inline Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]> (v1)
* dri_util: remove ALLOW_RGB10_CONFIGS option (v2)Marek Olšák2018-01-102-5/+2
| | | | | | | | This is unused because it's for libGL/libEGL, not drivers. v2: i965 was wrong, because it used dri_util instead of its own config. Reviewed-by: Tapani Pälli <[email protected]>
* swr/rast: switch win32 jit format to COFFTim Rowley2018-01-101-2/+2
| | | | | | Allows for call-stack and exception handling for jitted functions. Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: don't use 32-bit gathers for elements < 32-bits in sizeTim Rowley2018-01-101-1/+60
| | | | | | | | Using a gather for elements less than 32-bits in size can cause pagefaults when loading the last elements in a page-aligned-sized buffer. Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: autogenerate named structs instead of literal structsTim Rowley2018-01-101-8/+15
| | | | | | Results in far smaller and useful IR output. Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: SIMD16 fetch shader jitter cleanupTim Rowley2018-01-101-720/+368
| | | | | | | | Bake in USE_SIMD16_BUILDER code paths (for USE_SIMD16_SHADER defined), remove USE_SIMD16_BUILDER define, remove deprecated psuedo-SIMD16 code paths. Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: shuffle header files for msvc pre-compiled header usageTim Rowley2018-01-1010-88/+143
| | | | Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: SIMD16 builder - cleanup naming (simd2 -> simd16)Tim Rowley2018-01-105-233/+239
| | | | Reviewed-by: Bruce Cherniak <[email protected]>
* glsl/linker: Safely generate mask of possible locationsIan Romanick2018-01-101-4/+5
| | | | | | | | | | If MaxAttribs were ever raised to 32, undefined behavior would occur. We had already gone to the effort (albeit incorrectly) handle this in one case, so fix them all. CID: 1369628 Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Alejandro Piñeiro <[email protected]>
* glsl/linker: Mark no locations as invalid instead of marking all locationsIan Romanick2018-01-101-1/+1
| | | | | | | | | | | | If max_index were ever 32, the linker would have marked all 32 locations as invalid instead of marking none of them as invalid. It's a good thing the maximum value actually set by any driver for MaxAttribs is 16. Found by inspection while investigating CID 1369628. Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Alejandro Piñeiro <[email protected]>
* glsl: Don't handle visit_stop in several ::accept methodsIan Romanick2018-01-101-3/+6
| | | | | | | | | All cases where the result could be non-visit_continue would have already returned. CID: 401351, 1224465, 1224466 Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Alejandro Piñeiro <[email protected]>
* glsl: Remove unnecessary assignments to typeIan Romanick2018-01-101-4/+0
| | | | | | | | | None of these are necessary because result->type is the only thing used outside the giant switch-statement. CID: 1230983, 1230984 Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Alejandro Piñeiro <[email protected]>
* nir: Silence unused parameter warningsIan Romanick2018-01-101-2/+2
| | | | | | | | | | | | | | | | In file included from src/compiler/nir/nir_opt_algebraic.c:4:0: src/compiler/nir/nir_search_helpers.h: In function ‘is_not_const’: src/compiler/nir/nir_search_helpers.h:118:59: warning: unused parameter ‘num_components’ [-Wunused-parameter] is_not_const(nir_alu_instr *instr, unsigned src, unsigned num_components, ^~~~~~~~~~~~~~ src/compiler/nir/nir_search_helpers.h:119:29: warning: unused parameter ‘swizzle ’ [-Wunused-parameter] const uint8_t *swizzle) ^~~~~~~ Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Alejandro Piñeiro <[email protected]>
* radv: Remove some typos.Bas Nieuwenhuizen2018-01-102-4/+4
| | | | Trivial.
* radv: Implement VK_EXT_discard_rectangles.Bas Nieuwenhuizen2018-01-105-6/+110
| | | | | | | | Tested with a modified deferred demo and no regressions in a 1.0.2 mustpass run. Reviewed-by: Samuel Pitoiset <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* radv: Add mapping between dynamic state mask and external enum.Bas Nieuwenhuizen2018-01-103-38/+79
| | | | | | | | | The EXT values are really large, e.g. VK_DYNAMIC_STATE_DISCARD_RECTANGLE_EXT = 1000099000, so 1 << value is not going to fit into a 32-bit mask. Reviewed-by: Samuel Pitoiset <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* amd/common: bump the number of available user SGPRS to 32 on GFX9Samuel Pitoiset2018-01-101-1/+3
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: remove radv_pipeline_layout::push_constant_stages fieldSamuel Pitoiset2018-01-102-3/+0
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* amd/common: do not rely on the pipeline for the push constants logicSamuel Pitoiset2018-01-103-9/+9
| | | | | | | | It makes more sense to rely on nir_intrinsic_load_push_constant instead of the pipeline layout. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv/gfx9: calculate the number of ES VGPRs for merged shadersSamuel Pitoiset2018-01-101-3/+10
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv/gfx9: enable LDS for GS only if the ES type is TESSamuel Pitoiset2018-01-101-1/+2
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* amd/common: determine the ES type (VS or TES) for the GS on GFX9Samuel Pitoiset2018-01-102-0/+9
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* i965/nir: lower TES PatchVerticesIn to a constant when a TCS is presentIago Toral Quiroga2018-01-101-4/+22
| | | | | | | | | | | | | When a TCS is present at link time we know the number of vertices in the patch and we can lower gl_PatchVerticesIn in the TesEval stage directly to a constant. We already have a pass for this that we use in the Vulkan pipeline, so we just reuse that. Notice that the GLSL linker also implements this optimization, which we are not removing because other drivers may still depend on it, so this should only be useful for OpenGL SPIR-V shaders for now. Reviewed-by: Jason Ekstrand <[email protected]>
* glsl: remove Lower{TCS,TES}PatchVerticesInIago Toral Quiroga2018-01-104-31/+4
| | | | | | | | | | | | Intel was the only user and now NIR can do the lowering. v2: do not try to handle it as a system value directly for the SPIR-V path. In GL we rather handle it as a uniform like we do for the GLSL path (Jason). v3: drop LowerTESPatchVerticesIn as well (Jason) Reviewed-by: Jason Ekstrand <[email protected]>
* i965: lower gl_PatchVerticesIn to a uniformIago Toral Quiroga2018-01-101-0/+8
| | | | | | | | | | | | | We want this here instead of nir_lower_system_values because for Vulkan we don't want this lowering to take place. v2: do not try to handle it as a system value directly for the SPIR-V path. In GL we rather handle it as a uniform like we do for the GLSL path (Jason). v3: do this also for the TessEval stage (Jason) Reviewed-by: Jason Ekstrand <[email protected]>
* i965/nir: add a helper to lower gl_PatchVerticesIn to a uniformIago Toral Quiroga2018-01-102-0/+27
| | | | | | | | | | | | v2: do not try to handle it as a system value directly for the SPIR-V path. In GL we rather handle it as a uniform like we do for the GLSL path (Jason). v3: - Remove the uniform variable, it is alwats -1 now (Jason) - Also do the lowering for the TessEval stage (Jason) Reviewed-by: Jason Ekstrand <[email protected]>
* r600: don't emit tes samplers/views when tes isn't activeRoland Scheidegger2018-01-102-0/+19
| | | | | | | | | | | | | | | | | | | | | | | | Similar to const buffers. The driver must not emit any tes-related state if tes is disabled, since the hw slots are all shared by VS, therefore it would overwrite them (the mesa state tracker might not do this, but it would be perfectly legal to do so). Nevertheless I think the dirty state tracking logic in the driver is fundamentally flawed when tes is disabled/enabled, since it looks to me like the VS (and TES) state would not get reemitted to the correct slots (if it's not dirty anyway). Unless I'm missing something... Theoretically, the overwrite problem could be solved by using non-overlapping resource slots for TES and VS (since we're not even close to using half the resource slots), but it wouldn't work for constant buffers nor samplers, and for VS would still need to propagate changes to both LS and VS, so probably not a useful idea. Unfortunately there's zero coverage of this with piglit, since all tessellation shader tests are just shader_runner tests, which are unsuitable for testing any kind of state dependency tracking issues (so I can't even quickly hack something up to proove it and fix it...). TCS otoh is just fine - like GS it has its own hw slots. Tested-by: Konstantin Kharlamov <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
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