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* anv/gen9: Optimize slice and subslice load balancing behavior.Francisco Jerez2019-08-124-0/+109
| | | | | | | | | | | | | | | See "i965/gen9: Optimize slice and subslice load balancing behavior." for the rationale. According to Jason, improves Aztec Ruins performance by 2.7%. Reviewed-by: Kenneth Graunke <[email protected]> (v1) v2: Undo CPU performance micro-optimization done in i965 and iris due to lack of data justifying it on anv. Use cmd_buffer_apply_pipe_flushes wrapper instead of emitting pipe control command directly. (Jason) Reviewed-by: Jason Ekstrand <[email protected]>
* lima/ppir: Add fddx and fddyAndreas Baierl2019-08-124-0/+60
| | | | | | | | Lower fddx and fddy and set the right bits in codegen. Signed-off-by: Andreas Baierl <[email protected]> Reviewed-by: Vasily Khoruzhick <[email protected]> Reviewed-by: Erico Nunes <[email protected]>
* radv: Enable VK_KHR_pipeline_executable_properties.Bas Nieuwenhuizen2019-08-122-1/+7
| | | | Reviewed-by: Dave Airlie <[email protected]>
* radv: Implement radv_GetPipelineExecutableStatisticsKHR.Bas Nieuwenhuizen2019-08-121-0/+103
| | | | Reviewed-by: Dave Airlie <[email protected]>
* radv: Implement radv_GetPipelineExecutableInternalRepresentationsKHR.Bas Nieuwenhuizen2019-08-121-5/+104
| | | | Reviewed-by: Dave Airlie <[email protected]>
* radv: Implement radv_GetPipelineExecutablePropertiesKHR.Bas Nieuwenhuizen2019-08-121-0/+111
| | | | Reviewed-by: Dave Airlie <[email protected]>
* radv: Keep shader info when needed.Bas Nieuwenhuizen2019-08-124-23/+36
| | | | | | | This allows enabling the shader info keeping on a per shader basis. Also disables the cache on a per shader basis. Reviewed-by: Dave Airlie <[email protected]>
* radv: Add VK_KHR_pipeline_executable_properties in disabled state.Bas Nieuwenhuizen2019-08-121-0/+1
| | | | | | So we can add the functions. Reviewed-by: Dave Airlie <[email protected]>
* radv: Use string for nir dumping.Bas Nieuwenhuizen2019-08-124-8/+29
| | | | | | Reviewed-by: Dave Airlie <[email protected]> Allows us to easily dump all nir shaders for combined variants in vega and simplifies ownership.
* radv: Get max workgroup size without nir.Bas Nieuwenhuizen2019-08-123-19/+28
| | | | Reviewed-by: Dave Airlie <[email protected]>
* radv: Add utility function to calculate max waves.Bas Nieuwenhuizen2019-08-122-8/+24
| | | | | | Not AC because a lot of it is data extraction out of radv structs. Reviewed-by: Dave Airlie <[email protected]>
* iris/gen9: Optimize slice and subslice load balancing behavior.Francisco Jerez2019-08-125-0/+110
| | | | | | | See "i965/gen9: Optimize slice and subslice load balancing behavior." for the rationale. Reviewed-by: Kenneth Graunke <[email protected]>
* intel/genxml: Add GT_MODE hashing defs for Gen9.Francisco Jerez2019-08-121-0/+17
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* i965/gen9: Optimize slice and subslice load balancing behavior.Francisco Jerez2019-08-125-6/+109
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The default pixel hashing mode settings used for slice and subslice load balancing are far from optimal under certain conditions (see the comments below for the gory details). The top-of-the-line GT4 parts suffer from a particularly severe performance problem currently due to a subslice load balancing issue. Fixing this seems to improve graphics performance across the board for most of the benchmarks in my test set, up to ~20% in some cases, e.g. from SKL GT4: unigine/valley: 3.44% ±0.11% gfxbench/gl_manhattan31: 3.99% ±0.13% gputest/pixmark_piano: 7.95% ±0.33% synmark/OglTexFilterAniso: 15.22% ±0.07% synmark/OglTexMem128: 22.26% ±0.06% Lower-end platforms are also affected by some subslice load imbalance to a lesser degree, especially during CCS resolve and fast clear operations, which are handled specially here due to rasterization ocurring in reduced CCS coordinates, which changes the semantics of the pixel hashing mode settings. No regressions seen during my tests on some SKL, KBL and BXT configurations. Additional benchmark reports welcome on any Gen9 platforms (that includes anything with Skylake, Broxton, Kabylake, Geminilake, Coffeelake, Whiskey Lake, Comet Lake or Amber Lake in your renderer string). P.S.: A similar problem is likely to be present on other non-Gen9 platforms, especially for CCS resolve and fast clear operations. Will follow-up with additional patches fixing the hashing mode for those once I have enough performance data to justify it. Reviewed-by: Kenneth Graunke <[email protected]>
* pan/midgard: Handle 64-bit address in mir_mask_of_read_componentsAlyssa Rosenzweig2019-08-121-1/+36
| | | | | | | This is a bit of a hack, but it'll hold us over until we have 64-bit support wired through. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* pan/midgard: Allocate separate spill indices for lowered movesAlyssa Rosenzweig2019-08-121-6/+4
| | | | | | This helps RA be slightly more reasonable. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* pan/midgard: Extend liveness analysis to trinary opsAlyssa Rosenzweig2019-08-121-6/+2
| | | | | | Fixes RA fails with multiple indirect SSBO writes. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* pan/midgard: Fix load/store pairingAlyssa Rosenzweig2019-08-121-9/+6
| | | | | | | | | | | This used a delicate hack to try to find indirect inputs and skip them as candidates for pairing. Let's use a better criterion -- no sources -- and pair based on that. We could do better, but that would require more complex data flow analysis than we're interested in doing here. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* pan/midgard: Implement nir_intrinsic_load_num_work_groupsAlyssa Rosenzweig2019-08-125-0/+21
| | | | | | Just a sysval to route through. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* pan/midgard: Implement some compute builtinsAlyssa Rosenzweig2019-08-121-0/+28
| | | | | | | We implement gl_WorkGroupID and gl_LocalInvocationID, which map to ld_compute_id with special sources. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* pan/midgard: Rename ld_global_id -> ld_compute_idAlyssa Rosenzweig2019-08-122-3/+3
| | | | | | It's used for more general loads within a compute shader. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* pan/midgard: Handle partial writes in liveness analysisAlyssa Rosenzweig2019-08-121-9/+5
| | | | | | | | | | | | | | | This allows liveness analysis within a loop to be more fine grained, fixing RA failures with partial spilled movs within a loop, as well as enabling a slight reduction of register pressure more generally: total registers in shared programs: 350 -> 347 (-0.86%) registers in affected programs: 12 -> 9 (-25.00%) helped: 3 HURT: 0 helped stats (abs) min: 1 max: 1 x̄: 1.00 x̃: 1 helped stats (rel) min: 25.00% max: 25.00% x̄: 25.00% x̃: 25.00% Signed-off-by: Alyssa Rosenzweig <[email protected]>
* pan/midgard: Dump "no spill"?Alyssa Rosenzweig2019-08-121-0/+3
| | | | Signed-off-by: Alyssa Rosenzweig <[email protected]>
* pan/midgard: Absorb nonexistance sourcesAlyssa Rosenzweig2019-08-121-0/+5
| | | | Signed-off-by: Alyssa Rosenzweig <[email protected]>
* pan/midgard: Pretty-print destinationsAlyssa Rosenzweig2019-08-121-5/+6
| | | | | | They're not "sources" but they follow the same conventions. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* pan/midgard: Pretty-print unitsAlyssa Rosenzweig2019-08-121-1/+24
| | | | | | | Since we are seeing some use of MIR post-scheduling, let's get this printed right. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* pan/midgard: Print mask in dumped MIRAlyssa Rosenzweig2019-08-121-1/+19
| | | | Signed-off-by: Alyssa Rosenzweig <[email protected]>
* pan/midgard: Add no_spill flagAlyssa Rosenzweig2019-08-122-6/+15
| | | | | | Hint for the RA to avoid infinite spilling loops. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* pan/midgard: Generalize mir_mask_of_read_componentsAlyssa Rosenzweig2019-08-121-11/+24
| | | | | | This now works for load/store and texture instructions as well as ALU. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* pan/midgard: Implement SSBO accessAlyssa Rosenzweig2019-08-122-11/+115
| | | | | | | | Just laying the groundwork. Reads and writes should be supported (both direct and indirect, either int or float, vec1/2/3/4), but no bounds checking is done at the moment. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* pan/midgard: Pipe uniform mask through when spillingAlyssa Rosenzweig2019-08-122-2/+30
| | | | | | | | This is a corner case that happens a lot with SSBOs. Basically, if we only read a few components of a uniform, we need to only spill a few components or otherwise we try to spill what we spilled and RA hangs. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* pan/midgard: Clamp sysval component countAlyssa Rosenzweig2019-08-122-5/+9
| | | | | | | We don't want to load a 128-bit sysval when 64-bits will do. Fixes RA failures with SSBO indirect writes. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* pan/midgard: Pass uploaded midgard_instruction throughAlyssa Rosenzweig2019-08-122-5/+7
| | | | | | We want to edit it after emission in some cases. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* pan/midgard: Allow sysval destination overrideAlyssa Rosenzweig2019-08-122-4/+10
| | | | | | | Sometimes a sysval is used to facilitate an instruction but is not the instruction itself. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost: Force flush every compute jobAlyssa Rosenzweig2019-08-121-0/+2
| | | | | | | | | This is of course suboptimal for performance, forcing each glDispatchCompute call to be submitted separately to the kernel and finish to completion. However, for the initial bring-up of compute jobs, this simplifies quite a bit. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost: Add SSBO system valueAlyssa Rosenzweig2019-08-123-0/+38
| | | | | | | | | | | | | | For each SSBO index we get from Gallium/NIR, we need two pieces of information in the shader: 1. The address of the SSBO in GPU memory. Within the shader, we'll be accessing it with raw memory load/store, so we need the actual address, not just an index. 2. The size of the SSBO. This is not strictly necessary, but at some point, we may like to do bounds checking on SSBO accesses. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* gallium/util: Add u_stream_outputs_for_vertices helperAlyssa Rosenzweig2019-08-121-0/+19
| | | | | | | | | | | | | | | | | | | This u_prim.h helper determines the number of outputs for stream output, given a particular primitive type and a vertex count. This is useful for statically calculating sizes of stream output buffers (i.e. when there is no geometry/tessellation shader in use). This helper will be used in Panfrost's transform feedback implementation, as you can probably guess since why else would I be submitting it.... See also dEQP's getTransformFeedbackOutputCount routine. v2: Simplify definition using new helpers, which also extends to non-ES2 primitive types (Eric). Signed-off-by: Alyssa Rosenzweig <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* radeonsi: remove the always_nir optionMarek Olšák2019-08-124-6/+2
| | | | tgsi_to_nir is no longer optional if NIR is enabled.
* radeonsi/nir: implement default tess level system valuesMarek Olšák2019-08-123-18/+45
| | | | Reviewed-by: Connor Abbott <[email protected]>
* compiler: add SYSTEM_VALUE_TESS_LEVEL_OUTER/INNER_DEFAULTMarek Olšák2019-08-124-0/+20
| | | | | | TCS system values for internal passthru TCS, needed by radeonsi NIR support Reviewed-by: Connor Abbott <[email protected]>
* gallium: add TGSI_SEMANTIC_DEFAULT_OUTER/INNER_LEVELMarek Olšák2019-08-125-12/+19
| | | | for radeonsi NIR support.
* tgsi_to_nir: handle tess level inner/outer varyingsMarek Olšák2019-08-121-0/+7
| | | | | | | | for internal radeonsi shaders Reviewed-By: Timur Kristóf <[email protected]> Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Connor Abbott <[email protected]>
* tgsi_to_nir: add support for the stencil FS outputMarek Olšák2019-08-121-5/+12
| | | | | | Reviewed-By: Timur Kristóf <[email protected]> Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Connor Abbott <[email protected]>
* tgsi_to_nir: add support for TEX_LZMarek Olšák2019-08-121-2/+9
| | | | | Reviewed-By: Timur Kristóf <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* compiler: add SYSTEM_VALUE_USER_DATA_AMDMarek Olšák2019-08-127-0/+23
| | | | for internal radeonsi shaders
* compiler: add shader_info.cs.user_data_components_amdMarek Olšák2019-08-123-0/+5
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* tgsi_to_nir: add basic compute shader supportMarek Olšák2019-08-121-0/+23
| | | | | | Reviewed-By: Timur Kristóf <[email protected]> Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Connor Abbott <[email protected]>
* tgsi_to_nir: add support for LOAD & STORE with SSBOs and imagesMarek Olšák2019-08-121-2/+310
| | | | | Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Connor Abbott <[email protected]>
* tgsi_to_nir: make setup_texture_info reusableMarek Olšák2019-08-121-36/+48
| | | | | Reviewed-By: Timur Kristóf <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* tgsi_to_nir: add support for TXF_LZMarek Olšák2019-08-121-4/+13
| | | | | | Reviewed-By: Timur Kristóf <[email protected]> Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Connor Abbott <[email protected]>
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