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* panfrost/midgard: Reorder to permit constant biasAlyssa Rosenzweig2019-06-262-67/+61
| | | | Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost/midgard: Add helper to encode constant biasAlyssa Rosenzweig2019-06-261-0/+34
| | | | Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost/midgard: Handle negative immediate biasAlyssa Rosenzweig2019-06-262-4/+5
| | | | Signed-off-by: Alyssa Rosenzweig <[email protected]>
* freedreno: correct batch_depends_on() logicRob Clark2019-06-261-1/+1
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno: drop unused arg from fd_batch_flush()Rob Clark2019-06-2612-23/+23
| | | | | | | The `force` arg has been unused for a while.. but apparently I forgot to garbage collect it. Signed-off-by: Rob Clark <[email protected]>
* st/glsl: fix silly regression finding gs/tes variantsTimothy Arceri2019-06-261-1/+1
| | | | | | Fixes: d19fe5e67a39 ("st/glsl: support clamping color outputs in compat for gs/tes") Reviewed-by: Ilia Mirkin <[email protected]>
* st/glsl: support clamping color outputs in compat for gs/tesTimothy Arceri2019-06-264-13/+60
| | | | | | | This support requires the driver to be a NIR driver as we use the NIR lowering pass to do the clamping. Reviewed-by: Kenneth Graunke <[email protected]>
* nir: add tess support to nir_lower_clamp_color_outputs()Timothy Arceri2019-06-261-0/+1
| | | | | | | This will be used to add compat profile support for higher GL versions. Reviewed-by: Kenneth Graunke <[email protected]>
* glsl: Fix round64 conversion functionSagar Ghuge2019-06-251-9/+12
| | | | | | | | | | | | | | | | | | | | Fix round64 function to handle round to nearest even cases specially with positive and negative numbers with fraction part 0.5. v2: 1) Simplify unused bits (Elie Tournier) Fixes: KHR-GL45.gpu_shader_fp64.builtin.round_dvec2 KHR-GL45.gpu_shader_fp64.builtin.round_dvec3 KHR-GL45.gpu_shader_fp64.builtin.round_dvec4 KHR-GL45.gpu_shader_fp64.builtin.roundeven_double KHR-GL45.gpu_shader_fp64.builtin.roundeven_dvec2 KHR-GL45.gpu_shader_fp64.builtin.roundeven_dvec3 KHR-GL45.gpu_shader_fp64.builtin.roundeven_dvec4 Signed-off-by: Sagar Ghuge <[email protected]> Reviewed-by: Elie Tournier <[email protected]> Acked-by: Anuj Phogat <[email protected]>
* panfrost/ci: Add RK3288 flipflops I don't want to deal with right nowAlyssa Rosenzweig2019-06-251-0/+6
| | | | Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost/ci: Update failures listAlyssa Rosenzweig2019-06-251-363/+3
| | | | | | | | A ton of tests were fixed by this series. A few were incorrectly passing before (QualityError, for instance) and now are explicitly failing. A few legitimate regressions but overwhelmingly positive. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost/ci: Set MESA_GLES_VERSION_OVERRIDE=3.0Alyssa Rosenzweig2019-06-251-0/+1
| | | | | | | | Fixes cube map tests due to disagreements between Mesa, dEQP, and the spec... Signed-off-by: Alyssa Rosenzweig <[email protected]> Cc: Tomeu Vizoso <[email protected]>
* panfrost/ci: Run full set of mipmap testsAlyssa Rosenzweig2019-06-251-3/+0
| | | | Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost: Advertise support for other 8-bit UNORM formatsAlyssa Rosenzweig2019-06-251-26/+15
| | | | Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost: Use pipe_surface->format directly in blitterAlyssa Rosenzweig2019-06-251-1/+1
| | | | Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost: Invert swizzle for renderingAlyssa Rosenzweig2019-06-251-2/+30
| | | | | | Fixes rendering to e.g. alpha textures. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost: Honour first_layer...last_layer when samplingAlyssa Rosenzweig2019-06-251-1/+3
| | | | Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost: Use the sampler_view target (not the textures)Alyssa Rosenzweig2019-06-251-2/+2
| | | | | | | u_blitter gets "special treatment" and uses this mechanism to cast cube maps to 2D textures in order to texelFetch them. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost/midgard: Assert guard texelFetch against cubemapsAlyssa Rosenzweig2019-06-251-0/+3
| | | | Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost: Zero pixels in any axis is zero pixels totalAlyssa Rosenzweig2019-06-251-1/+1
| | | | | | Multiplication, not addition, so switch the logic operator. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost: Respect mip level when wallpaperingAlyssa Rosenzweig2019-06-251-1/+7
| | | | | | | Fixes DATA_INVALID_FAULT raised when wallpapering while rendering to a mipmap. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost/midgard: Fixup NIR texture opAlyssa Rosenzweig2019-06-251-0/+8
| | | | | | | In a vertex shader, a tex op should map to txl, as there *must* be a LOD given to the hardware (implicitly or explicitly). Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost: Support (non-)seamless cube mapsAlyssa Rosenzweig2019-06-253-4/+5
| | | | | | | Identify the seamless cubemap bit and passthrough the Gallium state rather than setting unconditionally. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost: Merge checksum buffer with main BOAlyssa Rosenzweig2019-06-255-47/+64
| | | | | | | | This is similar to the AFBC merge; now all (non-imported) buffers use a common backing buffer. Reenables checksumming, eliminating a performance regression. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost/decode: Limit MRT blend countAlyssa Rosenzweig2019-06-251-3/+8
| | | | | | | I thought I already fixed this. Maybe that was a dream...? Then again, I might be dreaming now. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost: Clamp tile coordinates before job submissionAlyssa Rosenzweig2019-06-251-0/+20
| | | | | | | Fixes TILE_RANGE_FAULT raised on some tests in dEQP-GLES3.functional.fbo.blit.* Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost: Use dedicated u_blitter context for wallpapersAlyssa Rosenzweig2019-06-253-19/+35
| | | | | | | | | | The main ctx->blitter instance should be reserved for blits originated from Gallium (like mipmap generation). Since wallpapering is conceptually different -- wallpaper blits can be triggered by Gallium blits -- the blitter pipes must be separate to avoid potential u_blitter recursion. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost: Sanity check layerAlyssa Rosenzweig2019-06-251-0/+1
| | | | | | | It doesn't make sense to try to render to multiple array elements at once. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost: Divide array_size by 6 for cubemapsAlyssa Rosenzweig2019-06-251-0/+1
| | | | | | | Addresses the disparity between Mali and Gallium definitions of array_size. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost: Use get_texture_address for framebuffer computationsAlyssa Rosenzweig2019-06-254-25/+28
| | | | | | | Allows for sharing some code as well as theoretically allowing cubemap rendering. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost: Merge AFBC slab with BO backingAlyssa Rosenzweig2019-06-255-91/+46
| | | | | | | | | | | | | | | Rather than tracking AFBC memory "specially", just use the same codepath as linear and tiled. Less things to mess up, I figure. This allows us to use the standard setup_slices() call with AFBC resources, allowing mipmapped AFBC resources. Unfortunately, we do have to disable AFBC (and checksumming) in the meantime to avoid functional regressions, as we don't know _a priori_ if we'll need to access a resource from software (which is not yet hooked up with AFBC) and we don't yet have routines to switch the layout of a BO at runtime. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost: Z/S can't be tiledAlyssa Rosenzweig2019-06-251-0/+3
| | | | | | | | As far as we know, Utgard-style tiling only works for color render targets, not depth/stencil, so ensure we don't try to tile it (rather than compress or plain old linear) and drive ourselves into a corner. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost: Enable mipmappingAlyssa Rosenzweig2019-06-251-1/+1
| | | | | | | Now the autogeneration of mipmaps is working (via u_blitter), we can finally enable mipmaps! Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost: Enable blittingAlyssa Rosenzweig2019-06-251-4/+0
| | | | | | | Now that all the prerequisites breaking u_blitter are fixed, we can finally hook up panfrost_blit. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost: Allow texelFetch for wallpaper blitsAlyssa Rosenzweig2019-06-251-3/+1
| | | | | | We just implemented the routine; we may as well use it. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost/midgard: Implement texelFetch (2D only)Alyssa Rosenzweig2019-06-251-6/+35
| | | | | | | | txf instructions can result from blits, so handle them rather than crash. Only works for 2D textures (not even 2D array texture) due to a register allocation constraint that may not be sorted for a while. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost: Skip flushes only for wallpapers, not any blitAlyssa Rosenzweig2019-06-251-1/+1
| | | | | | | We need the flush from u_blitter for a normal blit (e.g. for mipmaps); it's only wallpaper-related blits that are special-cased. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost: Handle generate_mipmap ourselvesAlyssa Rosenzweig2019-06-252-0/+55
| | | | | | | | | | | | | To avoid interference with the wallpaper code, we need to do some state tracking when generating mipmaps. In particular, we need to mark the generated layers as invalid before generating the mipmap, so we don't try to backblit them if they already had content. Likewise, we need to flush both before and after generating a mipmap since our usual set_framebuffer_state flushing isn't quite there yet. Ideally better optimizations would save the flush but I digress. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost: Disable mipmapping if necessaryAlyssa Rosenzweig2019-06-251-0/+16
| | | | | | | | If a mipfilter is not set, it's legal to have an incomplete mipmap; we should handle this accordingly. An "easy way out" is to rig the LOD clamps. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* intel/blorp: Disable sampler state prefetching on Gen11Kenneth Graunke2019-06-251-0/+4
| | | | | | | | | | | | | | | Sampler state prefetching is broken on Gen11, and WA_160668216 says to disable it. Apparently sampler state prefetching also has basically zero impact on performance, so we don't need to worry there. i965, anv, and iris already handle this correctly, but we missed BLORP. Ideally the kernel should globally disable this by writing SARCHKMD, at which point we wouldn't have to worry about it. But let's be defensive and handle it ourselves too. v2: separate out from BTP workaround in case we change that eventually Reviewed-by: Anuj Phogat <[email protected]> [v1]
* anv/descriptor_set: Only write texture swizzles if we have an image viewJason Ekstrand2019-06-251-1/+1
| | | | | | | | | When immutable samplers are set we call write_image_view with a NULL image view. This causes issues on IVB where we have to fake texture swizzling. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110999 Fixes: d2aa65eb18 "anv: Emulate texture swizzle in the shader when..."
* virgl: add VIRGL_DEBUG_XFERChia-I Wu2019-06-253-4/+9
| | | | | | | | When set, do as requested and skip any transfer optimization. Signed-off-by: Chia-I Wu <[email protected]> Reviewed-By: Gert Wollny <[email protected]> Reviewed-By: Alexandros Frantzis <[email protected]>
* virgl: add VIRGL_DEBUG_SYNCChia-I Wu2019-06-253-1/+20
| | | | | | | | When set, wait after every each flush. Signed-off-by: Chia-I Wu <[email protected]> Reviewed-By: Gert Wollny <[email protected]> Reviewed-By: Alexandros Frantzis <[email protected]>
* virgl: fix the value of VIRGL_DEBUG_BGRA_DEST_SWIZZLEChia-I Wu2019-06-252-8/+10
| | | | | | | | | | | | VIRGL_DEBUG_BGRA_DEST_SWIZZLE should use bit 3. Make some cosmetic changes as well. Fixes: a478e56fbd33fa23503b63d41265a1c2f3253ed2 virgl: Add debug flag to bypass driconf to enable the BGRA tweaks Signed-off-by: Chia-I Wu <[email protected]> Reviewed-By: Gert Wollny <[email protected]> Reviewed-By: Alexandros Frantzis <[email protected]>
* radv: rename and re-document cache flush flagsSamuel Pitoiset2019-06-2510-58/+62
| | | | | | | SMEM and VMEM caches are L0 on gfx10. Ported from RadeonSI. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: set DISABLE_CONSTANT_ENCODE_REG to 1 for Raven2Samuel Pitoiset2019-06-253-1/+9
| | | | | | | Ported from RadeonSI, will be emitted for GFX10 too. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: clear CMASK layers instead of the whole buffer on GFX8Samuel Pitoiset2019-06-257-18/+35
| | | | | | | | | | This reduces the size of fill operations needed to clear CMASK for layered color textures. GFX9 unsupported for now. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: clear FMASK layers instead of the whole buffer on GFX8Samuel Pitoiset2019-06-258-10/+31
| | | | | | | | | | This reduces the size of fill operations needed to clear FMASK for layered color textures. GFX9 unsupported for now. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: always initialize levels without DCC as fully expandedSamuel Pitoiset2019-06-251-17/+15
| | | | | | | This fixes a rendering issue with RoTR/DXVK. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* i965: leaking of upload-BO with push constantsSergii Romantsov2019-06-251-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In case of any enabled VS members from: uses_firstvertex, uses_baseinstance, uses_drawid, uses_is_indexed_draw leaks may happens. Call gen6_upload_push_constants allocates stage_stat->push_const_bo. It than takes pointer from push_const_bo to draw_params_bo (in the call brw_prepare_shader_draw_parameters by brw_upload_data) and do reference which finally haven't got unreferenced. Fixes leak: 136 bytes in 1 blocks are definitely lost in loss record 6 of 13 at 0x4C31B25: calloc (in /usr/lib/valgrind/vgpreload_memcheck-amd64-linux.so) by 0xC2B64B7: bo_alloc_internal (brw_bufmgr.c:596) by 0xC2B6748: brw_bo_alloc (brw_bufmgr.c:672) by 0xC314BB3: brw_upload_space (intel_upload.c:88) by 0xC2EBBC5: gen6_upload_push_constants (gen6_constant_state.c:155) by 0xC9E4FA6: gen9_upload_vs_push_constants (genX_state_upload.c:3300) by 0xC2E0EDA: check_and_emit_atom (brw_state_upload.c:540) by 0xC2E0EDA: brw_upload_pipeline_state (brw_state_upload.c:659) by 0xC2E0FF1: brw_upload_render_state (brw_state_upload.c:681) by 0xC2C5D2D: brw_draw_single_prim (brw_draw.c:1052) by 0xC2C62CB: brw_draw_prims (brw_draw.c:1175) by 0xC488AD1: vbo_exec_vtx_flush (vbo_exec_draw.c:386) by 0xC485270: vbo_exec_FlushVertices_internal (vbo_exec_api.c:652) Reviewed-by: Lionel Landwerlin <[email protected]> Reported-by: Yevhenii Kolesnikov <[email protected]> Signed-off-by: Sergii Romantsov <[email protected]>
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