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* v3d: Enable NaN propagation in the VS and CS as well.Eric Anholt2018-05-174-4/+12
| | | | Fixes piglit vs-isnan-*.shader_test at the expense of gl-1.0-spot-light.
* i965/blorp: Disable BLORP clear color updatesNanley Chery2018-05-171-2/+4
| | | | | | | With the previous patches, we now update the indirect clear color buffer every time the clear color changes. Avoid redundant updates. Reviewed-by: Jason Ekstrand <[email protected]>
* intel/blorp: Add a NO_UPDATE_CLEAR_COLOR batch flagNanley Chery2018-05-172-2/+9
| | | | | | | | | Allow callers to handle updating the indirect clear color buffer themselves. This can reduce the number of clear color updates in the case where a caller performs multiple fast clears with the same clear color. Reviewed-by: Jason Ekstrand <[email protected]>
* i965/blorp: Also skip the fast clear if the clear color differsNanley Chery2018-05-171-4/+3
| | | | | | | | If the aux state is CLEAR and clear color value has changed, only the surface state must be updated. The bit-pattern in the aux buffer is exactly the same. Reviewed-by: Jason Ekstrand <[email protected]>
* i965/clear: Drop a stale comment in fast_clear_depthNanley Chery2018-05-171-4/+0
| | | | | | | | | This comment made more sense when it was above the calls to intel_miptree_slice_set_needs_depth_resolve(). We stopped using these functions at commit 554f7d6d02931ea45653c8872565d21c1678a6da ("i965: Move depth to the new resolve functions"). Reviewed-by: Jason Ekstrand <[email protected]>
* i965: Update the indirect buffer in set_clear_colorNanley Chery2018-05-172-37/+13
| | | | | | | | | | | | | | | | | | | | | For depth buffers, we avoid fast-clearing if the aux_state is already CLEAR. We do the same for color buffers only if the clear color doesn't change. We require that the clear colors match because, in that case, we don't update the indirect clear color outside of BLORP. Update the indirect clear color for color buffers as well. We'll enable the same depth buffer optimization for color buffers in a later patch. Note that we're now actually updating the indirect clear color twice in the case where we use BLORP to perform the fast-clear. This is only temporary. In later patches, we'll prevent BLORP from performing the update. v2: Add more context to the commit message (Topi). Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/clear: Remove an early return in fast_clear_depthNanley Chery2018-05-171-5/+0
| | | | | | | | | | | Reduce complexity and allow the next patch to delete some code. With this change, clear operations will still be skipped and setting the aux_state will cause no side-effects. Remove the associated comment which implies an early return. Reviewed-by: Rafael Antognolli <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* i965: Use set_clear_color for depth miptreesNanley Chery2018-05-173-19/+2
| | | | | | | Reduce code duplication now and prevent it in the following commits. Reviewed-by: Topi Pohjolainen <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* Revert "i965: Make the miptree clear color setter take a gl_color_union"Nanley Chery2018-05-173-7/+6
| | | | | | | | | | | | This reverts commit 1d94aa19877fb702ffacacde28ad7253cce72c97. The next patch will make depth miptrees use the clear color setter that was originally being used for color miptrees. Go back to using the isl_color_value parameter because it's the same type as the fast_clear_color field used by color and depth miptrees. Reviewed-by: Topi Pohjolainen <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* i965/miptree: Unify aux buffer allocationNanley Chery2018-05-172-142/+82
| | | | | | | | | | There isn't much that changes between the aux allocation functions. Remove the duplicated code. v2: Inline the switch statement (Jason). Reviewed-by: Topi Pohjolainen <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* i965: Prepare to delete intel_miptree_alloc_ccs()Nanley Chery2018-05-173-15/+16
| | | | | | | | | | | | We're going to delete intel_miptree_alloc_ccs() in the next commit. With that in mind, replace the use of this function in do_single_blorp_clear() with intel_miptree_alloc_aux() and move the delayed allocation logic to it's callers. v2: Duplicate the delayed allocation comment (Topi Pohjolainen). Reviewed-by: Topi Pohjolainen <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* i965/miptree: Drop the mt param from alloc_aux_bufferNanley Chery2018-05-171-5/+4
| | | | | | Drop an unused parameter. Reviewed-by: Jason Ekstrand <[email protected]>
* i965/miptree: Drop the alloc_flags param from alloc_aux_bufferNanley Chery2018-05-171-15/+14
| | | | | | | We have enough information to determine the optimal flags internally. Reviewed-by: Topi Pohjolainen <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* i965/miptree: Drop the name param from alloc_aux_bufferNanley Chery2018-05-171-5/+4
| | | | | | A name of "aux-miptree" should be sufficient. Reviewed-by: Jason Ekstrand <[email protected]>
* i965/miptree: Initialize the indirect clear color to zeroNanley Chery2018-05-171-11/+22
| | | | | | | | | | | | | | | | | | | | | | | | The indirect clear color isn't correctly tracked in intel_miptree::fast_clear_color. The initial value of ::fast_clear_color is zero, while that of the indirect clear color is undefined. Topi Pohjolainen discovered this issue with MCS buffers. This issue is apparent when fast-clearing an MCS buffer for the first time with glClearColor = {0.0,}. Although the indirect clear color is undefined, the initial aux state of the MCS is CLEAR and the tracked clear color is zero, so we avoid updating the indirect clear color with {0.0,}. Make the indirect clear color match the initial value of ::fast_clear_color. Note: although we only have to drop HiZ's BO_ALLOC_BUSY flag for gen10+, we also drop it pre-gen10 to keep things simple. We add this flag back for pre-gen10 in a later patch. v2: Add a note about dropping HiZ's BO_ALLOC_BUSY flag (Topi). Reviewed-by: Topi Pohjolainen <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* i965/miptree: Add and use a memset option in alloc_aux_bufferNanley Chery2018-05-171-37/+31
| | | | | | | | Add infrastructure for initializing the clear color BO. intel_miptree_init_mcs is no longer needed with change. Reviewed-by: Topi Pohjolainen <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* i965/miptree: Zero-initialize CCS_D buffersNanley Chery2018-05-171-6/+4
| | | | | | | | | | | | | | | | | | Before this patch, the aux_state was actually AUX_INVALID because the BO was never defined. This was fine on single slice miptrees because we would fast-clear the resource right after creation. For multi-slice miptrees on SKL+ however, this results in undefined behavior when accessing a non-base slice. Here's a specific example: 1) Fast clear level 0 * Undefined CCS_D buffer allocated in "PASS_THROUGH" state. * Level 0 transitions to the CLEAR state. 2) Render to level 1 * Level 1 may have a 2-bit pattern of 2's. * Rendering with a 2 in the CCS is undefined. Cc: <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* i965/miptree: Fix handling of uninitialized MCS buffersNanley Chery2018-05-171-7/+7
| | | | | | | | | | | | | Before this patch, if we failed to initialize an MCS buffer, we'd end up in a state in which the miptree thinks it has an MCS buffer, but doesn't. We also leaked the clear_color_bo if it existed. With this patch, we now free the miptree aux buffer resources and let intel_miptree_alloc_mcs() know that the MCS buffer no longer exists. Cc: <[email protected]> Reviewed-by: Tapani Pälli <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* radv: only declare the ESGS rings for pre GFX9 chipsSamuel Pitoiset2018-05-171-4/+10
| | | | | | | GFX9 uses LDS instead. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: allow to print GPU info with RADV_DEBUG=infoSamuel Pitoiset2018-05-172-0/+5
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: do not emit unnecessary ES output storesSamuel Pitoiset2018-05-171-3/+23
| | | | | | | | | | | | | | | | | | | | | | GFX9: Totals from affected shaders: SGPRS: 472 -> 464 (-1.69 %) VGPRS: 576 -> 584 (1.39 %) Code Size: 45432 -> 44324 (-2.44 %) bytes Max Waves: 40 -> 40 (0.00 %) VI: SGPRS: 720 -> 720 (0.00 %) VGPRS: 728 -> 728 (0.00 %) Code Size: 45348 -> 43992 (-2.99 %) bytes Max Waves: 120 -> 120 (0.00 %) This affects Rise of Tomb Raider and the three Vulkan demos that use a geometry shader (geometryshader, deferredshadows and viewportarray). Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: do not emit unnecessary GS output storesSamuel Pitoiset2018-05-171-0/+7
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: only pass the global BO list at submit time if enabledSamuel Pitoiset2018-05-171-2/+6
| | | | | | | | That way the winsys might use a faster path when the global BO list is NULL. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: remove the radv_finishme() when compiling shadersSamuel Pitoiset2018-05-171-4/+0
| | | | | | | | Having an entrypoint different than "main" doesn't mean we have multiple shaders per module. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: remove radv_device::llvm_supports_spillSamuel Pitoiset2018-05-173-7/+1
| | | | | | | It's always true. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* mesa: add glUniform*ui{v} support to display listsTimothy Arceri2018-05-171-33/+17
| | | | | | | Fixes: a017c7ecb7ae "mesa: display list support for uint uniforms" Reviewed-by: Marek Olšák <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=78097
* radeonsi: create .gitignoreDieter Nützel2018-05-161-0/+2
| | | | | Signed-off-by: Dieter Nützel <[email protected]> Signed-off-by: Marek Olšák <[email protected]>
* ac/llvm: use amdgcn.tbuffer.store instead of SI.tbuffer.store intrinsicDave Airlie2018-05-171-32/+60
| | | | | | Drop the use of the old intrinsic. Reviewed-by: Marek Olšák <[email protected]>
* v3d: Fix wiring filters to NEAREST for 32-bit texture returns.Eric Anholt2018-05-161-1/+1
| | | | Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104626
* v3d: Enable the driver by default.Eric Anholt2018-05-161-1/+1
| | | | | Now that we have a stabilized ABI and a fairly conformant driver, turn it on.
* v3d: Rename driver functions from vc5 to v3d.Eric Anholt2018-05-1629-1533/+1533
| | | | This is the final step of the driver rename.
* v3d: Rename the driver files from "vc5" to "v3d".Eric Anholt2018-05-1650-126/+126
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* v3d: Rename the vc5_dri.so driver to v3d_dri.so.Eric Anholt2018-05-1626-80/+80
| | | | | | This allows the driver to load against the merged kernel DRM driver. In the process, rename most of the build system variables and gallium plumbing functions.
* v3d: Switch the vc5 driver to using the finalized V3D UABI.Eric Anholt2018-05-169-234/+39
| | | | | | In the process of merging to the kernel, I renamed the driver to the general product line's name (since we have both vc5 and vc6 supported already). Since the ABI is finalized, move the header to include/drm-uapi.
* svga: fix incompatible bind flags at buffer validation timeCharmaine Lee2018-05-161-2/+7
| | | | | | | | | | | | At buffer resource validation time, if the resource handle is not yet created and if the initial buffer bind flags and the tobind flags are incompatible, just use the tobind flags to create the resource handle. On the other hand, if the bind flags are compatible, we can combine the bind flags for the resource handle creation. Fixes piglit gl-3.1-buffer-bindings crash. Reviewed-by: Brian Paul <[email protected]>
* mesa: cast the GLenum16 to GLint to avoid compile warning on androidjenny.q.cao2018-05-161-1/+1
| | | | | | | | | | | | Cast the enum to GLint to avoid the compile warning: /src/mesa/main/get.c:3005:19: warning: comparison of constant -32768 with expression of type 'GLenum16' (aka 'unsigned short') is always false -Wtautologicalia-constant-out-of-range-compare Tests: compilation without this warning Signed-off-by: jenny.q.cao <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* etnaviv: Fix missing rnndb file in tarballsStuart Young2018-05-162-0/+2
| | | | | | | | | | | | | | | Seems that when the rnndb files for etniviv were updated/included back in Nov 2017, hw/texdesc_3d.xml.h was missed from Makefile.sources and meson.build. This was all during the conversion to meson, so it apears to have slipped through the cracks. As such, this file has been missing from the official tarballs since inclusion in Mesa, so the git trees and tarballs differ. Found due to lintian errors in the Debian packages. Fixes: f1e1c60ff6 ("etnaviv: Update from rnndb") Cc: [email protected] Reviewed-by: Christian Gmeiner <[email protected]>
* gallium/hud: add frametime graph (v2)Matthias Groß2018-05-153-1/+38
| | | | | | | | | Thanks for your comment. This version has an additional boolean in the fps_info struct to distinguish between fps and frame time calculation. The struct is initialised in the respecting install functions for this purpose. Signed-off-by: Marek Olšák <[email protected]>
* eg/compute: Use reference counting to handle compute memory pool.Jan Vesely2018-05-152-12/+7
| | | | | | | | | | | | | Use pipe_reference to release old RAT surfaces. RAT surface adds a reference to pool bo, so use reference counting for pool->bo as well. v2: Use the same pattern for both defrag paths Drop confusing comment CC: <[email protected]> Signed-off-by: Jan Vesely <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* gallivm: Use alloca_undef with array type instead of alloca_arrayRoland Scheidegger2018-05-161-28/+33
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use a single allocation of array type instead of the old-style array allocation for the temp and immediate arrays. Probably only makes a difference if they aren't used indirectly (so, if we used them solely because there's too many temps or immediates). In this case the sroa and early-cse passes can sometimes do some optimizations which they otherwise cannot. (As a side note, for the temp reg array, we actually really should use one allocation per array id, not just one for everything.) Note that the instcombine pass would actually promote such allocations to single alloc of array type as well, but it's too late for some artificial shaders we've seen to help (we don't want to run instcombine at the beginning due to its cost, hence would need another sroa/cse pass after instcombine). sroa/early-cse help there because they can actually eliminate all of the huge shader, reducing it to a single const output (don't ask...). (Interestingly, instcombine also removes all the bitcasts we do on that allocation for single-value gathering, and in the end directly indexes into the single vector elements, which according to spec is only semi-valid, but this happens regardless. Another thing instcombine also does is use inbound GEPs, which is probably something we should do manually as well - for indirectly indexed reg files llvm may not be able to figure it out on its own, but we should be able to guarantee all pointers are always inbound. In any case, by the looks of it using single allocation with array type seems to be the right thing to do even for ordinary shaders.) No piglit change. Reviewed-by: Jose Fonseca <[email protected]>
* radv: add generated files to .gitignore(s)Dieter Nützel2018-05-151-0/+1
| | | | | Signed-off-by: Dieter Nützel <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]>
* spirv: fix visiting inner loops with same break/continue blockSamuel Pitoiset2018-05-151-0/+13
| | | | | | | | | | | | | | | | | | | | | | | | We should stop walking through the CFG when the inner loop's break block ends up as the same block as the outer loop's continue block because we are already going to visit it. This fixes the following assertion which ends up by crashing in RADV or ANV: SPIR-V parsing FAILED: In file ../src/compiler/spirv/vtn_cfg.c:381 block->node.link.next == NULL 0 bytes into the SPIR-V binary This also fixes a crash with a camera shader from SteamVR. v2: make use of vtn_get_branch_type() and add an assertion Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106090 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106504 CC: 18.0 18.1 <[email protected]> Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* mesa/st: handle vert_attrib_mask in nir case tooRob Clark2018-05-151-7/+7
| | | | | | | | | | | Note, actually fixes 9987a072cb, but the problems don't show up until 19a91841c3. Fixes: 19a91841c3 st/mesa: Use Array._DrawVAO in st_atom_array.c. Fixes: 9987a072cb st/mesa: Make the input_to_index array available. Signed-off-by: Rob Clark <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Mathias Fröhlich <[email protected]>
* cso: check count == 0 in cso_set_vertex_buffersMarek Olšák2018-05-151-0/+3
| | | | | | | | The code didn't expect that, leading to crashes. Fixes: 86d63b53a20a747e "gallium: remove aux_vertex_buffer_slot code" Tested-by: Michel Dänzer <[email protected]>
* vc5: use util_copy_framebuffer_stateRob Clark2018-05-151-12/+2
| | | | | Signed-off-by: Rob Clark <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* vc4: use util_copy_framebuffer_stateRob Clark2018-05-151-12/+2
| | | | | Signed-off-by: Rob Clark <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* freedreno/a5xx: remove fd5_shader_stateobjRob Clark2018-05-153-23/+10
| | | | | | Extra level of indirection that serves no purpose. Signed-off-by: Rob Clark <[email protected]>
* freedreno/a4xx: remove fd4_shader_stateobjRob Clark2018-05-153-23/+10
| | | | | | Extra level of indirection that serves no purpose. Signed-off-by: Rob Clark <[email protected]>
* freedreno/a3xx: remove fd3_shader_stateobjRob Clark2018-05-153-26/+13
| | | | | | Extra level of indirection that serves no purpose. Signed-off-by: Rob Clark <[email protected]>
* freedreno: fence should hold a ref to pipeRob Clark2018-05-151-3/+4
| | | | | | | | | | | | | | | | | | | | | | | Since the fence can outlive the context, and all it really needs to wait on a fence is the pipe, use the new fd_pipe reference counting to hold a ref to the pipe and drop the ctx pointer. This fixes a crash seen with (for example) glmark2: #0 fd_pipe_wait_timeout (pipe=0xbf48678b3cd7b32b, timestamp=0, timeout=18446744073709551615) at freedreno_pipe.c:101 #1 0x0000ffffbdf75914 in fd_fence_finish (pscreen=0x561110, ctx=0x0, fence=0xc55c10, timeout=18446744073709551615) at ../src/gallium/drivers/freedreno/freedreno_fence.c:96 #2 0x0000ffffbde154e4 in dri_flush (cPriv=0xb1ff80, dPriv=0x556660, flags=3, reason=__DRI2_THROTTLE_SWAPBUFFER) at ../src/gallium/state_trackers/dri/dri_drawable.c:569 #3 0x0000ffffbecd8b44 in loader_dri3_flush (draw=0x558a28, flags=3, throttle_reason=__DRI2_THROTTLE_SWAPBUFFER) at ../src/loader/loader_dri3_helper.c:656 #4 0x0000ffffbecbc36c in glx_dri3_flush_drawable (draw=0x558a28, flags=3) at ../src/glx/dri3_glx.c:132 #5 0x0000ffffbecd91e8 in loader_dri3_swap_buffers_msc (draw=0x558a28, target_msc=0, divisor=0, remainder=0, flush_flags=3, force_copy=false) at ../src/loader/loader_dri3_helper.c:827 #6 0x0000ffffbecbcfc4 in dri3_swap_buffers (pdraw=0x5589f0, target_msc=0, divisor=0, remainder=0, flush=1) at ../src/glx/dri3_glx.c:587 #7 0x0000ffffbec98218 in glXSwapBuffers (dpy=0x502bb0, drawable=2097154) at ../src/glx/glxcmds.c:840 #8 0x000000000040994c in CanvasGeneric::update (this=0xfffffffff400) at ../src/canvas-generic.cpp:114 #9 0x0000000000411594 in MainLoop::step (this=this@entry=0x5728f0) at ../src/main-loop.cpp:108 #10 0x0000000000409498 in do_benchmark (canvas=...) at ../src/main.cpp:117 #11 0x00000000004071b0 in main (argc=<optimized out>, argv=<optimized out>) at ../src/main.cpp:210 Signed-off-by: Rob Clark <[email protected]>
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