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* glx: use GLX_ALIAS for glXGetProcAddressEmil Velikov2017-01-181-13/+4
| | | | | | Use the macro, rather than open-coding it. Signed-off-by: Emil Velikov <[email protected]>
* mesa: make use of HAVE_FUNC_ATTRIBUTE_ALIAS macroEmil Velikov2017-01-184-13/+7
| | | | | | | | | | | We must make sure that xserver has an equivalent one-line change to its configure.ac as the glx/glapi headers get copied over. Then again, xserver does _not_ seem to set HAVE_ALIAS to begin with so one might want to look into that first. Cc: Adam Jackson <[email protected]> Signed-off-by: Emil Velikov <[email protected]>
* glx: remove always false ifdef GLX_NO_STATIC_EXTENSION_FUNCTIONSEmil Velikov2017-01-181-5/+0
| | | | | | | Quick search through git history (of both mesa and xserver) hows no instances where this was ever set. Signed-off-by: Emil Velikov <[email protected]>
* etnaviv: Fake occlusion query capabilityWladimir J. van der Laan2017-01-181-2/+3
| | | | | | | | | | | | | This enables the PIPE_CAP_OCCLUSION_QUERY capability without adding an occlusion query type. This is necessary to get Mesa to report desktop GL 2.0 support (to run exciting things such as ioq3's OpenGL 2 renderer), and should be valid because exposing the capability does not guarantee that any counters are actually implemented. Signed-off-by: Wladimir J. van der Laan <[email protected]> Reviewed-by: Christian Gmeiner <[email protected]>
* etnaviv: add flags parameter to texture barrierChristian Gmeiner2017-01-181-1/+1
| | | | | | Fixes compile warning introduced by commit a1c848. Signed-off-by: Christian Gmeiner <[email protected]>
* etnaviv: handle PIPE_CAP_TGSI_FS_FBFETCHChristian Gmeiner2017-01-181-0/+1
| | | | | | Fixes compile warning introduced by commit ee3ebe. Signed-off-by: Christian Gmeiner <[email protected]>
* gallivm: (trivial) fix copy/paste bug with big endian codeRoland Scheidegger2017-01-181-2/+4
| | | | | | 8bd67a35c50e68c21aed043de11e095c284d151a introduced using undefined variable on big endian archs due to copy/paste bug. (compile hack tested only)
* configure.ac: Revert recent HAVE_LLVM changes.Jose Fonseca2017-01-185-12/+12
| | | | | | | | | | | | | | | | This reverts changes 903eb09b5fb78d47d0f8a4bdf826a113ca2aff40..1a0aa468f354f0ee94dd383cd40ae915584624aa: Tobias Droste (5): configure.ac: Rename MESA_LLVM to FOUND_LLVM configure.ac: Only set LLVM_LIBS if LLVM is used configure.ac: Only define HAVE_LLVM if LLVM is used configure.ac: Set and use HAVE_GALLIUM_LLVM define configure.ac: Don't check LLVM version in gallium_require_llvm They break scons build, and I'm not convinced this is the right fix. In particular changing HAVE_LLVM in the C code is something I'd rather avoid no matter what. So it's better to discuss without the pressure of broken builds.
* vulkan: automake: do not use EXTRA_DIST in a conditionalEmil Velikov2017-01-181-1/+1
| | | | | | | Otherwise the file might not end up in the tarball. Fixes: dbd677efb42 "vulkan: add API registry" Signed-off-by: Emil Velikov <[email protected]>
* configure.ac: Set and use HAVE_GALLIUM_LLVM defineTobias Droste2017-01-185-12/+12
| | | | | | | | | | | | Gallium code used HAVE_LLVM to check if it needs to compile code for LLVM in header and source files. With the new logic HAVE_LLVM is always set. Use extra define to figure out if LLVM is used. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=99010 Signed-off-by: Tobias Droste <[email protected]>
* gallivm: Cleanup USE_MCJIT.Jose Fonseca2017-01-181-10/+25
| | | | | | | Split USE_MCJIT macro dual nature into a separate constant time define and a run-time variable. Reviewed-by: Emil Velikov <[email protected]>
* i965: Don't map/unmap in brw_print_program_cache on LLC platforms.Kenneth Graunke2017-01-171-2/+4
| | | | | | | | | | | We have a persistent mapping. Don't map it a second time or try to unmap it. Just use the pointer. This most likely would wreak havoc except that this code is unused (it's only called from an if (0) debug block). Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eduardo Lima Mitev <[email protected]>
* i965: Move program cache printing to brw_program_cache.c.Kenneth Graunke2017-01-173-57/+49
| | | | | | | | It makes sense to put a function which prints out the entire contents of the program cache in the file that implements the program cache. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eduardo Lima Mitev <[email protected]>
* i965: Make a helper for finding an existing shader variant.Kenneth Graunke2017-01-177-85/+68
| | | | | | | | | We had five copies of the same "walk the cache and look for an existing shader variant for this program" code. Now we have one helper function that returns the key. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eduardo Lima Mitev <[email protected]>
* glsl: Make copy propagation not panic when it sees an intrinsic.Kenneth Graunke2017-01-171-4/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A number of games have large arrays of constants, which we promote to uniforms. This introduces copies from the uniform array to the original temporary array. Normally, copy propagation eliminates those copies, making everything refer to the uniform array directly. A number of shaders in "Deus Ex: Mankind Divided" recently exposed a limitation of copy propagation - if we had any intrinsics (i.e. image access in a compute shader), we weren't able to get rid of these copies. That meant that any variable indexing remained on the temporary array rather being moved to the uniform array. i965's scalar backend currently doesn't support indirect addressing of temporary arrays, which meant lowering it to if-ladders. This was horrible. According to Marek, on radeonsi/GCN, "F1 2015" uses 64% less spilled-temp-array memory. On i965/Skylake: total instructions in shared programs: 13362954 -> 13329878 (-0.25%) instructions in affected programs: 43745 -> 10669 (-75.61%) helped: 12 HURT: 0 total cycles in shared programs: 248081010 -> 245949178 (-0.86%) cycles in affected programs: 4597930 -> 2466098 (-46.37%) helped: 12 HURT: 0 total spills in shared programs: 9493 -> 9507 (0.15%) spills in affected programs: 25 -> 39 (56.00%) helped: 0 HURT: 1 total fills in shared programs: 12127 -> 12197 (0.58%) fills in affected programs: 110 -> 180 (63.64%) helped: 0 HURT: 1 Helps Deus Ex: Mankind Divided. The one shader with hurt spills/fills is from Tomb Raider at Ultra settings, but that same shader has a -39.55% reduction in instructions and -14.09% reduction in cycle counts, so it seems like a win there as well. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Timothy Arceri <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965: Make DCE set null destinations on messages with side effects.Kenneth Graunke2017-01-171-13/+41
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | (Co-authored by Matt Turner.) Image atomics, for example, return a value - but the shader may not want to use it. We assigned a useless VGRF destination. This seemed harmless, but it can actually be quite harmful. The register allocator has to assign that VGRF to a real register. It may assign the same actual GRF to the destination of an instruction that follows soon after. This results in a write-after-write (WAW) dependency, and stall. A number of "Deus Ex: Mankind Divided" shaders use image atomics, but don't use the return value. Several of these were hitting WAW stalls for nearly 14,000 (poorly estimated) cycles a pop. Making dead code elimination null out the destination avoids this issue. This patch cuts one shader's estimated cycles by -98.39%! Removing the message response should also help with data cluster bandwidth. On Skylake: (instruction counts remain identical) total cycles in shared programs: 255413890 -> 248081010 (-2.87%) cycles in affected programs: 12019948 -> 4687068 (-61.01%) helped: 24 HURT: 10 v2: Make can_omit_write independent of can_eliminate (Curro). Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Francisco Jerez <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965: Combine some dead code elimination NOP'ing code.Kenneth Graunke2017-01-171-8/+1
| | | | | | | | | | | | | | | | | | | | | | | | In theory we might have incorrectly NOP'd instructions that write the flag, but where that flag value isn't used, and yet the instruction either writes the accumulator or has side effects. I don't believe any such instructions exist, so this is mostly a code cleanup. Curro pointed out that FS_OPCODE_FB_WRITE has a null destination and actually writes the flag on Gen4-5 to dynamically decide whether to write some payload data. The hunk removed in this patch might have NOP'd it, except that we don't actually mark flags_written() in the IR, so it doesn't think the flag is touched at all. That's sketchy, but it means it wouldn't hit this today (though there are likely other problems!). v2: Properly replace the inst->regs_written() check in the second hunk with the flag being live (mistake caught by Curro). Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Francisco Jerez <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965: Make DCE explicitly not eliminate any control flow instructions.Kenneth Graunke2017-01-171-3/+2
| | | | | | | | | | | | | | | | | | | According to Matt, the dead code pass explicitly avoided IF and WHILE because on Sandybridge, these could have conditional modifiers and null destination registers. Normally, those instructions use BAD_FILE for the destination register. Nowadays, we don't do that anymore, so we could technically drop these checks. However, it's clearer to explicitly leave control flow instructions alone, so change it to the more generic !inst->is_control_flow(). This should have no actual change. [This patch implements review feedback from Curro and Matt.] Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Francisco Jerez <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* radv: disable vertex reuse when writing viewport indexDave Airlie2017-01-181-0/+2
| | | | | | | | This fixes some issues we'd hit later if using viewport indexes. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: add support for layered clears (v2)Dave Airlie2017-01-181-6/+22
| | | | | | | | | | | Just always use the layer clear pipelines, the overhead of emitting the layer shouldn't be too large. v2: Bas suggested we always use it. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv/ac: split part of llvm compile into a separate functionDave Airlie2017-01-181-11/+22
| | | | | | | | This is needed to have common code for gs copy shader emission. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Edward O'Callaghan <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv/ac: switch an if to switchDave Airlie2017-01-181-4/+9
| | | | | | | | makes it easier to add other shader stages. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Edward O'Callaghan <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: add support for writing layer/viewport index (v2)Dave Airlie2017-01-183-4/+25
| | | | | | | | | | | This just adds the infrastructure to allow writing layer and viewport index. It's just a first patch out of the geom shader tree, and doesn't do much on its own. v2: add missing if statement change (Bas) Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* ac/debug: Decrease num_dw for type 2 NOP's.Bas Nieuwenhuizen2017-01-171-0/+1
| | | | | | | Otherwise we read past the end of the buffer. Signed-off-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: for the tess barrier, only use emit_waitcnt on SI and LLVM 3.9+Marek Olšák2017-01-171-2/+5
| | | | | | Cc: 17.0 13.0 <[email protected]> Reviewed-by: Edward O'Callaghan <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* st/vdpau: remove the delayed rendering hack(v1.1)Nayan Deshmukh2017-01-176-141/+52
| | | | | | | | | | the hack was introduced to avoid an extra copying but now with dri3 we don't need it anymore v1.1: rebasing Signed-off-by: Nayan Deshmukh <[email protected]> Acked-by: Christian König <[email protected]>
* st/vdpau: use dri3 to directly send the buffer to X(v2)Nayan Deshmukh2017-01-172-27/+33
| | | | | | | | | | | | this avoids an extra copy which occurs in case of dri2 v1.1: fallback to dri2 if dri3 fails to initialize v2: add PIPE_BIND_SCANOUT to output buffers as they will be send to X server directly (Michel) Suggested-by: Christian König <[email protected]> Tested-by: Andy Furniss <[email protected]> Signed-off-by: Nayan Deshmukh <[email protected]>
* vl/dri3: use external texture as back buffers(v4)Nayan Deshmukh2017-01-172-17/+114
| | | | | | | | | | | | | | | | | | | | | dri3 allows us to send handle of a texture directly to X so this patch allows a state tracker to directly send its texture to X to be used as back buffer and avoids extra copying v2: use clip width/height to display a portion of the surface v3: remove redundant variables, fix wrapping, rename variables handle vaapi path v3.1: we need clip_width/height for every frame so we don't need to maintain it for each buffer instead use a global variable v4: In case of single gpu we can cache the buffers as applications use constant number of buffer and we can avoid calls to present extension for every frame Reviewed and Suggested-by: Leo Liu <[email protected]> Acked-by: Christian König <[email protected]> Tested-by: Andy Furniss <[email protected]> Signed-off-by: Nayan Deshmukh <[email protected]>
* anv: set UAV coherence required bit when neededIago Toral Quiroga2017-01-171-0/+51
| | | | | | | | | | | | | | | | The same we do in the OpenGL driver (comment copied from there). This is required to ensure that we execute the fragment shader stage when side-effects (such as image or ssbo stores) are present but there are no color writes. I found this while writing a test to check rendering to a framebuffer without attachments where the fragment shader does not produce any color outputs but writes to an image via imageStore(). Without this patch the fragment shader does not execute and the image is not written, which is not correct. Reviewed-by: Jason Ekstrand <[email protected]>
* anv: increase ANV_MAX_STATE_SIZE_LOG2 limit to 1 MBSamuel Iglesias Gonsálvez2017-01-172-2/+2
| | | | | | | | | | | | | | | Fixes crash in dEQP-VK.ubo.random.all_shared_buffer.48 due to a fragment shader code bigger than 128 kB. This patch increases the allocation size limit to 1 MB. v2: - Increase it to 1 MB (Jason) - Increase device->instruction_block_pool allocation size in anv_device.c (Jason) Signed-off-by: Samuel Iglesias Gonsálvez <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* nv50/ir: optimize shl + andIlia Mirkin2017-01-161-0/+11
| | | | | | | | | | | | | | | | | Address loading can often end up as shl + shr + shl combinations. The latter two are equal shifts, which get converted into an and mask. However if the previous shl is more than the mask is trying to remove (in terms of low bits), we can just remove the and entirely. This reduces some large shaders by as many as 3% of instructions (out of 2K). total instructions in shared programs : 6495509 -> 6491076 (-0.07%) total gprs used in shared programs : 954621 -> 954623 (0.00%) local gpr inst bytes helped 0 0 1014 1014 hurt 0 2 0 0 Signed-off-by: Ilia Mirkin <[email protected]>
* nvc0: enable FBFETCH with a special slot for color buffer 0Ilia Mirkin2017-01-169-6/+172
| | | | | | | | | | | | We don't need to support all the color buffers for advanced blend, just cb0. For Fermi, we use the special binding slots so that we don't overlap with user textures, while Kepler+ gets a dedicated position for the fb handle in the driver constbuf. This logic is only triggered when a FBFETCH is actually present so it should be a no-op most of the time. Signed-off-by: Ilia Mirkin <[email protected]>
* st/mesa: add support for advanced blend when fb can be fetched fromIlia Mirkin2017-01-164-8/+37
| | | | | | | | | This implements support for emitting FBFETCH ops, using the existing lowering pass for advanced blend logic, and disabling hw blend when advanced blending is enabled. Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium: add flags parameter to texture barrierIlia Mirkin2017-01-1614-16/+24
| | | | | | | | This is so that we can differentiate between flushing any framebuffer reading caches from regular sampler caches. Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium: add PIPE_CAP_TGSI_FS_FBFETCHIlia Mirkin2017-01-1617-2/+20
| | | | | Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium: add FBFETCH opcode to retrieve the current sample valueIlia Mirkin2017-01-163-2/+15
| | | | | Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* mesa: allow BlendBarrier to be used without support for full fb fetchIlia Mirkin2017-01-161-1/+2
| | | | | | | | The extension spec is not currently published, so it's a bit premature to require it for BlendBarrier usage. Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* glsl: avoid treating fb fetches as output reads to be loweredIlia Mirkin2017-01-161-1/+1
| | | | | Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* radv/meta: split color renderpass creation out.Dave Airlie2017-01-171-38/+49
| | | | | | | | This is just prep work for layered clears, it doesn't change anything. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: Support multiple devices.Bas Nieuwenhuizen2017-01-162-44/+19
| | | | | | | | | | | | | | Pretty straightforward. Also deleted the big comment block as it is a pretty standard pattern for filling in arrays. Also removed the error message on non-existent devices, as getting 7 errors printed to the console each time you enumerate the devices is pretty confusing. v2: Add constant for number of DRM devices. Signed-off-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* radv: Get physical device from radv_device instead of the instance.Bas Nieuwenhuizen2017-01-169-49/+50
| | | | | Signed-off-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* nvc0: true up exposing of the HW_METRIC_QUERY_GROUP for maxwellIlia Mirkin2017-01-161-2/+2
| | | | | | | This had been updated in one place but not the other. Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]>
* radv/ac: use ctx->voidt in more places. (v2)Dave Airlie2017-01-171-11/+11
| | | | | | | | | Just noticed this while in the area. v2: one replacement was incorrect. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv/meta: consolidate the depth stencil clear renderpassesDave Airlie2017-01-172-41/+48
| | | | | | | | We only need one per samples (maybe not even that), reduce all the unneeded ones. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* nv50/ir: handle new DDIV op which will be used for double divisionsIlia Mirkin2017-01-161-0/+3
| | | | | | | The existing lowering is in place to lower that to RCP + MUL, or fancier things down the line if necessary. Signed-off-by: Ilia Mirkin <[email protected]>
* tgsi: add DDIV instructionNicolai Hähnle2017-01-164-1/+17
| | | | | | | | | Double-precision division, to allow more precision than a DRCP + DMUL sequence. Reviewed-by: Roland Scheidegger <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: fix R600_DEBUG=nooptvariantNicolai Hähnle2017-01-161-1/+1
| | | | | Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Vedran Miletić <[email protected]>
* i965: Make BLORP disable the NP Z PMA stall fix.Kenneth Graunke2017-01-161-0/+4
| | | | | | | | This may fix GPU hangs on Gen8. I don't know if it does though. Cc: [email protected] Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* i965: Enable OpenGL 4.5 on Haswell.Kenneth Graunke2017-01-162-2/+2
| | | | | | | | Everything is in place and the test results look solid. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Samuel Iglesias Gonsálvez <[email protected]>
* radeonsi: implement GL_FIXED vertex formatMarek Olšák2017-01-163-7/+20
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
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