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* mesa/st: add nir pass for lowering builtin uniformsRob Clark2016-05-173-0/+278
| | | | | Signed-off-by: Rob Clark <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* scons: gallium: link against nir as neededEmil Velikov2016-05-175-1/+5
| | | | | | | | ... otherwise we'll produce uncomplete binaries with introduction of NIR as alternative IR with next commits. Signed-off-by: Emil Velikov <[email protected]> Acked-by: Jose Fonseca <[email protected]>
* i965/fs: Add an allow_spilling flag to brw_compile_fsJason Ekstrand2016-05-177-20/+28
| | | | | | | | | This allows us to disable spilling for blorp shaders since blorp state setup doesn't handle spilling. Without this, blorp fails hard if you run with INTEL_DEBUG=spill. Reviewed-by: Francisco Jerez <[email protected]> Tested-by: Francisco Jerez <[email protected]>
* nvc0/ir: fix shared atomic lowering to preserve shared memory locationIlia Mirkin2016-05-171-10/+8
| | | | | | | | | | We were always doing atomics on shared memory location 0 instead of the originally supplied location. Make sure to pass through the original symbol and any indirection. Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]> Cc: [email protected] # note: expect minor conflict
* freedreno/ir3: fix compiler warningRob Clark2016-05-171-0/+1
| | | | Signed-off-by: Rob Clark <[email protected]>
* nir/validate: dump annotated shader with error msgsRob Clark2016-05-171-1/+62
| | | | | | | | | Log all the errors, and at the end dump the shader w/ error annotations to make it easier to see where the problems are. Signed-off-by: Rob Clark <[email protected]> Reviewed-by: Eduardo Lima Mitev <[email protected]> Reviewed-by: Connor Abbott <[email protected]>
* nir/validate: assert() -> validate_assert()Rob Clark2016-05-171-126/+128
| | | | | | | Prep work for next patch. Signed-off-by: Rob Clark <[email protected]> Reviewed-by: Connor Abbott <[email protected]>
* nir/print: add support for print annotationsRob Clark2016-05-172-1/+35
| | | | | | | | | | | | | | | Caller can pass a hashtable mapping NIR object (currently instr or var, but I guess others could be added as needed) to annotation msg to print inline with the shader dump. As the annotation msg is printed, it is removed from the hashtable to give the caller a way to know about any unassociated msgs. This is used in the next patch, for nir_validate to try to associate error msgs to nir_print dump. Signed-off-by: Rob Clark <[email protected]> Reviewed-by: Eduardo Lima Mitev <[email protected]> Reviewed-by: Connor Abbott <[email protected]>
* i965: Expose OpenGL 4.2 for gen8+Alejandro Piñeiro2016-05-172-2/+2
| | | | | | | | ARB_vertex_attrib_64bit was the only feature missing. v2: we can expose 4.2 instead of 4.1 (Ian Romanick) Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Enable ARB_vertex_attrib_64bit for gen8+Alejandro Piñeiro2016-05-171-0/+1
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* i965: take care of doubles when lowering VS inputsJuan A. Suarez Romero2016-05-173-1/+16
| | | | | | | Input attributes can require 2 vec4 or 1 vec4 depending on whether they are double-precision or not. Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: calculate first non-payload GRF using attrib slotsJuan A. Suarez Romero2016-05-173-1/+3
| | | | | | | | | | When computing where the first non-payload GRF starts, we can't rely on the number of attributes, as each attribute can be using 1 or 2 slots depending on whether they are a dvec3/4 or other. Instead, we need to use the number of slots used by the attributes. Reviewed-by: Kenneth Graunke <[email protected]>
* i965/vec4: use attribute slots to calculate URB read lengthJuan A. Suarez Romero2016-05-171-3/+9
| | | | | | | | | | Do not use total attributes because a dvec3/dvec4 attribute requires two slots. So rather use total attribute slots. v2: do not use loop to calculate required attribute slots (Kenneth Graunke) Reviewed-by: Kenneth Graunke <[email protected]>
* i965: take care of doubles when remapping VS attributesJuan A. Suarez Romero2016-05-171-15/+11
| | | | | | | Double-precision types require 1 slot in VUE for double and dvec2, and 2 slots for anything else. Reviewed-by: Kenneth Graunke <[email protected]>
* nir: add double input bitmapJuan A. Suarez Romero2016-05-172-0/+3
| | | | | | This bitmap tracks which input attributes are double-precision. Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: shuffle 32bits into 64bits for doublesJuan A. Suarez Romero2016-05-171-0/+8
| | | | | | | | | | | | | | | | VS Thread Payload handles attributes in URB as vec4, no matter if they are actually single or double precision. So with double-precision types, value ends up in the registers split in 32bits chunks, in different positions. We need to shuffle the chunks to get the doubles correctly. v2: * Extra blank line. Add { } on if body (Ian Romanick) * Use dest directly (Kenneth Graunke) Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: half exec_size when dealing with 64 bits attributesAlejandro Piñeiro2016-05-171-2/+19
| | | | | | | | | | | | | The HW has a restriction that only vertical stride may cross register boundaries. Until now this was only handled on VGRFs at rw_reg_from_fs_reg, but it is also needed for attributes. v2: * Remove reference to commit id on commit message (Juan Suarez) * Simplify code that compute final exec_size (Ian Romanick) * Use REG_SIZE on that same code (Kenneth Graunke) Reviewed-by: Kenneth Graunke <[email protected]>
* i965: passthru formats cannot be used width edge flag enabledAlejandro Piñeiro2016-05-171-0/+20
| | | | | | Add an assertion to detect this case. Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Configure how to store *64*PASSTHRU vertex componentsAntia Puentes2016-05-171-0/+35
| | | | | | | | | | | | | | | | | | | | | | | | | From the Broadwell specification, structure VERTEX_ELEMENT_STATE description: "When SourceElementFormat is set to one of the *64*_PASSTHRU formats, 64-bit components are stored in the URB without any conversion. In this case, vertex elements must be written as 128 or 256 bits, with VFCOMP_STORE_0 being used to pad the output as required. E.g., if R64_PASSTHRU is used to copy a 64-bit Red component into the URB, Component 1 must be specified as VFCOMP_STORE_0 (with Components 2,3 set to VFCOMP_NOSTORE) in order to output a 128-bit vertex element, or Components 1-3 must be specified as VFCOMP_STORE_0 in order to output a 256-bit vertex element. Likewise, use of R64G64B64_PASSTHRU requires Component 3 to be specified as VFCOMP_STORE_0 in order to output a 256-bit vertex element." Uses 128-bits to write double and dvec2 vertex elements, and 256-bits for dvec3 and dvec4 vertex elements. Signed-off-by: Juan A. Suarez Romero <[email protected]> Signed-off-by: Antia Puentes <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: get the proper vertex surface type for doubles on gen8+Alejandro Piñeiro2016-05-171-3/+27
| | | | | | | | | | This commit adds support for PASSTHRU format when pushing double-precision attributes. Check glarray->Doubles in order to know if we should choose a format that does a conversion to float, or just passthru the 64-bit double. Reviewed-by: Kenneth Graunke <[email protected]>
* nvc0/ir: make sure out-of-bounds buffer loads/atomics get a 0 resultIlia Mirkin2016-05-171-1/+26
| | | | | Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]>
* glsl: make reserved_varying_slot() staticTimothy Arceri2016-05-171-1/+1
| | | | Reviewed-by: Dave Airlie <[email protected]>
* glsl: include per-patch varyings when generating reserved slot bitfieldTimothy Arceri2016-05-171-3/+6
| | | | Reviewed-by: Dave Airlie <[email protected]>
* glsl: don't incorrectly eliminate patches with explicit locationsTimothy Arceri2016-05-171-1/+2
| | | | | | | These varying have a separate location domain from per-vertex varyings and need to be handled separately. Reviewed-by: Dave Airlie <[email protected]>
* glsl: remove remainings tabs in link_varyings.cppTimothy Arceri2016-05-171-2/+2
| | | | Reviewed-by: Dave Airlie <[email protected]>
* glsl: fix location and component packing validation on patchesTimothy Arceri2016-05-172-1/+3
| | | | | | | These varyings have a separate location domain from per-vertex varyings and need to be handled separately. Reviewed-by: Dave Airlie <[email protected]>
* i965: Enable ARB_shader_precision on Gen8+.Kenneth Graunke2016-05-161-0/+1
| | | | | | | | | | | | | I recently fixed a bug in the Piglit tests: https://lists.freedesktop.org/archives/piglit/2016-May/019802.html With that patch in place, we pass all the tests. So, turn it on. We could probably expose this earlier than Gen8, but the extension says that OpenGL 4.0 is required, and all of our tests are written against GLSL 4.00 (which is only supported on Gen8+). Signed-off-by: Kenneth Graunke <[email protected]>
* vl/dri: Move the DRI3 check out of sources include into C.Jose Fonseca2016-05-162-5/+5
| | | | | | Fixes SCons build. Trivial. Built locally with SCons and autotools.
* st/vdpau: add dri3 supportLeo Liu2016-05-161-1/+5
| | | | | | Signed-off-by: Leo Liu <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Christian König <[email protected]>
* vl/dri3: implement functions for get and set timestampLeo Liu2016-05-161-6/+53
| | | | | | Signed-off-by: Leo Liu <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Christian König <[email protected]>
* vl/dri3: handle PresentCompleteNotify eventLeo Liu2016-05-161-1/+27
| | | | | | | | and get timestamp calculated based on the event's reply Signed-off-by: Leo Liu <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Christian König <[email protected]>
* st/va: add dri3 supportLeo Liu2016-05-161-1/+5
| | | | | | Signed-off-by: Leo Liu <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Christian König <[email protected]>
* vl/dri3: implement DRI3 BufferFromPixmapLeo Liu2016-05-161-3/+113
| | | | | | | | | | | | We also need render to the front buffer of temporary X pixmap, this is the case of when we using opengl as video out for vaapi. the basic implementation is to pass pixmap ID to X server, and then X will return dma-buf fd, we will get the buffer object through this dma-buf fd. Signed-off-by: Leo Liu <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Christian König <[email protected]>
* vl/dri3: add support for resizingLeo Liu2016-05-161-4/+13
| | | | | | | | | When drawable size changed, PresentConfigureNotify event will be emitted, by handling the event to re-allocate resized buffer. Signed-off-by: Leo Liu <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Christian König <[email protected]>
* vl/dri3: implement funciton for get dirty areaLeo Liu2016-05-161-2/+9
| | | | | | | | This will clear presentation area not covered by video content Signed-off-by: Leo Liu <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Christian König <[email protected]>
* vl/dri3: implement function for flush frontbufferLeo Liu2016-05-161-2/+30
| | | | | | | | | Request drawable content in pixmap by calling DRI3 PresentPixmap, and handle PresentIdleNotify event. Signed-off-by: Leo Liu <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Christian König <[email protected]>
* vl/dri3: add back buffers supportLeo Liu2016-05-161-2/+185
| | | | | | | | | | | This implements DRI3 PixmapFromBuffer. Create buffer objects, and associate it to a dma-buf fd, and then pass this fd with a pixmap ID to X server for creating pixmap object; also add a function for wait events. Signed-off-by: Leo Liu <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Christian König <[email protected]>
* vl/dri3: implement flushing for queued eventsLeo Liu2016-05-161-0/+36
| | | | | | | | also place holder for present events handling Signed-off-by: Leo Liu <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Christian König <[email protected]>
* vl/dri3: register present eventsLeo Liu2016-05-161-0/+27
| | | | | | Signed-off-by: Leo Liu <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Christian König <[email protected]>
* vl/dri3: set drawable geometryLeo Liu2016-05-161-0/+35
| | | | | | Signed-off-by: Leo Liu <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Christian König <[email protected]>
* vl/dri3: add DRI3 support and implement create and destroyLeo Liu2016-05-163-0/+208
| | | | | | | | | | | | | Required functions into place for implementation, create screen with device fd returned from X server, also bail out to DRI2 with certain conditions. v2: -organize the error out path (Axel) -squash previous patch 1 and 2 into one (Emil) Signed-off-by: Leo Liu <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Christian König <[email protected]>
* mesa/version.c: enable cull distance in version check.Dave Airlie2016-05-171-1/+1
| | | | | Reviewed-by: Ilia Mirkin <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* glsl/linker: Include the interface name for input and output blocksIan Romanick2016-05-161-1/+16
| | | | | | | | | On my oes_shader_io_blocks branch, this fixes 71 dEQP-GLES31.functional.program_interface_query.* tests. Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Cc: [email protected]
* glsl/linker: Use canonical format for ARB_program_interface_query spec quotesIan Romanick2016-05-161-49/+51
| | | | | Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: check tcs for NULL dereferenceMark Janes2016-05-161-3/+5
| | | | | | | | Coverity issue 1361544 found an instance where the tcs variable is checked for NULL, but unconditionally dereferenced later in the same function. Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Mark is_lossless_compressed_aux UNUSED to silence warning.Matt Turner2016-05-161-1/+1
| | | | Used only in assert().
* genxml: Use llroundf() and store to appropriate type.Matt Turner2016-05-161-2/+2
| | | | | | | Both functions return uint64_t, so I expect the masking/shifting should be done on 64-bit types. Reviewed-by: Kristian Høgsberg <[email protected]>
* nir: Mark nir_start_block()/nir_impl_last_block() with returns_nonnull.Matt Turner2016-05-161-4/+5
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* util: Add ATTRIBUTE_RETURNS_NONNULL.Matt Turner2016-05-161-0/+6
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* clover: grid_offset should be padded with 0 not 1Jan Vesely2016-05-161-1/+1
| | | | | Signed-off-by: Jan Vesely <[email protected]> Reviewed-by: Francisco Jerez <[email protected]>
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