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* i965/screen: Sanity check that all formats we advertise are useableJason Ekstrand2018-06-071-4/+20
* i965/screen: Use RGBA non-sRGB formats for imagesJason Ekstrand2018-06-071-0/+9
* i965/screen: Return false for unsupported formats in query_modifiersJason Ekstrand2018-06-071-2/+14
* i965/screen: Refactor query_dma_buf_formatsJason Ekstrand2018-06-071-12/+13
* intel/isl: Add bounds-checking assertions for the format_info tableJason Ekstrand2018-06-071-8/+16
* intel/isl: Add bounds-checking assertions in isl_format_get_layoutJason Ekstrand2018-06-072-12/+22
* anv: Set fence/semaphore types to NONE in impl_cleanupJason Ekstrand2018-06-071-13/+16
* nir: Add global invocation id intrinsic.Plamena Manolova2018-06-072-0/+5
* i965: Require softpin support for Cannonlake and later.Kenneth Graunke2018-06-061-0/+10
* i965: Allocate VMA in userspace for full-PPGTT systems.Kenneth Graunke2018-06-061-1/+1
* intel/blorp: Emit VF cache invalidates for 48-bit bugs with softpin.Kenneth Graunke2018-06-063-5/+51
* nir: add opt_if_loop_terminator()Timothy Arceri2018-06-071-0/+68
* nir: move ends_in_break() helper to nir_loop_analyze.hTimothy Arceri2018-06-072-13/+13
* radv: fix Coverity no effect control flow issueTimothy Arceri2018-06-071-1/+1
* intel/blorp: Don't vertex fetch directly from clear valuesJason Ekstrand2018-06-061-44/+41
* dri: add missing 16bits formats mappingLionel Landwerlin2018-06-071-0/+16
* nir: Look into uniform structs for samplers when counting num_textures.Eric Anholt2018-06-061-12/+44
* v3d: Work around GFXH-1461/GFXH-1689 by using CLEAR_TILE_BUFFERS.Eric Anholt2018-06-061-10/+17
* v3d: Enable the new NIR bitfield operation lowering paths.Eric Anholt2018-06-061-2/+19
* nir: Add lowering for nir_op_bit_count.Eric Anholt2018-06-062-0/+38
* nir: Add lowering for nir_op_bitfield_reverse.Eric Anholt2018-06-062-1/+48
* nir: Add an ALU lowering pass for mul_high.Eric Anholt2018-06-065-0/+171
* nir: Add lowering for find_lsb.Eric Anholt2018-06-062-0/+6
* nir: Add lowering for ifind_msb to ufind_msb.Eric Anholt2018-06-062-0/+6
* nir: Add lowering from ibitfield_extract/ubitfield_extract to shifts.Eric Anholt2018-06-062-0/+19
* nir: Add lowering for bitfieldInsert without using bfi.Eric Anholt2018-06-062-0/+19
* egl: remove wayland-egl now that we're using libwayland-eglEric Engestrom2018-06-067-516/+0
* egl: rewire the build systems to use libwayland-eglEric Engestrom2018-06-065-19/+8
* glsl: Take 'double' as reserved after GLSL ES 1.0zhaowei yuan2018-06-051-1/+1
* r300g/swtcl: make pipe_context uploaders use malloc'd memory as beforeMarek Olšák2018-06-051-3/+6
* intel/eu: Use a struct copy instead of a memcpyJason Ekstrand2018-06-051-1/+1
* radv: Use correct color format for fast clearsPhilip Rebohle2018-06-051-2/+2
* v3d: Be more explicit about include directory from our generated code.Eric Anholt2018-06-053-2/+5
* radv: Do not hardcode fast clear formats.Bas Nieuwenhuizen2018-06-051-180/+73
* intel/tools: add intel_sanitize_gpu to EXTRA_DISTScott D Phillips2018-06-051-0/+2
* util/tests/vma: Fix warning c++11-narrowingScott D Phillips2018-06-051-1/+1
* util: tests: vma test depends on C++11 supportScott D Phillips2018-06-051-2/+5
* glx: Fix number of property values to read in glXImportContextEXTMichel Dänzer2018-06-051-1/+1
* anv: intel: add softpin flag on imported BOsLionel Landwerlin2018-06-051-0/+2
* autotools: add missing android file to packageEric Engestrom2018-06-051-0/+1
* mesa: Make sure that imm draws are flushed before other draws execute.Mathias Fröhlich2018-06-054-65/+56
* virgl: use bits in caps set v2[email protected]2018-06-052-0/+6
* virgl: add shader offset alignment to to v2 caps struct[email protected]2018-06-053-1/+4
* i965: Prepare batchbuffer module for softpin support.Kenneth Graunke2018-06-042-3/+39
* i965: Add virtual memory allocator infrastructure to brw_bufmgr.Kenneth Graunke2018-06-042-1/+286
* i965: Disable internal CCS for shadows of multi-sampled windowsJason Ekstrand2018-06-041-1/+10
* i965/miptree: Rename a parameter to create_for_dri_imageJason Ekstrand2018-06-042-4/+4
* intel/eu: Switch to a logical state stackJason Ekstrand2018-06-043-126/+72
* intel/eu: Set flag [sub]register number differently for 3srcJason Ekstrand2018-06-041-3/+10
* intel/eu: Copy fields manually in brw_next_insnJason Ekstrand2018-06-041-1/+94
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