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* radv: execute external subpass barriers after ending subpassesSamuel Pitoiset2019-02-041-2/+2
| | | | | | | | | Outgoing dependencies (ie. external) should happen after the subpass. This doesn't change anything for subpass resolves as we already make sure that attachments are shader readable. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: accumulate all ingoing external dependencies to the first subpassSamuel Pitoiset2019-02-041-0/+4
| | | | | | | In case two or more subpasses declare ingoing external dependencies. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: handle subpass dependencies correctlySamuel Pitoiset2019-02-041-6/+6
| | | | | | | | | The different masks should be accumulated. For example if two subpasses declare an outgoing dependency (ie. dst == VK_SUBPASS_EXTERNAL). Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: track if subpasses have color attachmentsSamuel Pitoiset2019-02-043-9/+7
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: add radv_render_pass_add_subpass_dep() helperSamuel Pitoiset2019-02-041-40/+38
| | | | | | | To share common code that handles subpass dependencies. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: move some render pass things to radv_render_pass_compile()Samuel Pitoiset2019-02-041-28/+38
| | | | | | | | radv_render_pass_compile() is common to vkCreateRenderPass() and vkCreateRenderPass2(). Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: handle final layouts at end of every subpass and render passSamuel Pitoiset2019-02-041-22/+38
| | | | | | | | That shouldn't change anything as we check if the last subpass id is the final subpass. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: determine the last subpass id for every attachmentsSamuel Pitoiset2019-02-042-0/+15
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: use the new attachments array when starting subpassesSamuel Pitoiset2019-02-041-12/+5
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: store the list of attachments for every subpassSamuel Pitoiset2019-02-047-55/+96
| | | | | | | | | This reworks how the depth stencil attachment is used for simplicity. This also introduces radv_render_pass_compile() helper that will be used for further optimizations. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: move subpass image transitions to radv_cmd_buffer_begin_subpass()Samuel Pitoiset2019-02-045-29/+27
| | | | | | | Instead of doing them in radv_cmd_buffer_set_subpass(). Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: add radv_cmd_buffer_begin_subpass() helperSamuel Pitoiset2019-02-041-12/+32
| | | | | | | | To unify some code in BeginRenderPass() and NextSubpass(). Based on Intel ANV driver. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: remove useless MAYBE_UNUSED in CmdBeginRenderPass()Samuel Pitoiset2019-02-041-1/+1
| | | | | | | Trivial. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: remove unused radv_render_pass_attachment::view_maskSamuel Pitoiset2019-02-042-11/+0
| | | | | | | Trivial. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: bail out when no image transitions will be performedSamuel Pitoiset2019-02-041-0/+3
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* wsi/display: add commentEric Engestrom2019-02-021-1/+1
| | | | | Signed-off-by: Eric Engestrom <[email protected]> Reviewed-by: Keith Packard <[email protected]>
* anv: Implement VK_EXT_buffer_device_addressJason Ekstrand2019-02-015-2/+67
| | | | Reviewed-by: Lionel Landwerlin <[email protected]>
* intel/fs: Implement nir_intrinsic_global_atomic_*Jason Ekstrand2019-02-018-0/+202
| | | | eviewed-by: Kenneth Graunke <[email protected]>
* intel/fs: Use SENDS for A64 writes on gen9+Jason Ekstrand2019-02-011-10/+23
| | | | eviewed-by: Kenneth Graunke <[email protected]>
* intel/fs: Implement load/store_global with A64 untyped messagesJason Ekstrand2019-02-017-1/+273
| | | | eviewed-by: Kenneth Graunke <[email protected]>
* intel/fs: Do the grf127 hack on SIMD8 instructions in SIMD16 modeJason Ekstrand2019-02-011-7/+6
| | | | | | | | | | | Previously, we only applied the fix to shaders with a dispatch mode of SIMD8 but the code it relies on for SIMD16 mode only applies to SIMD16 instructions. If you have a SIMD8 instruction in a SIMD16 shader, neither would trigger and the restriction could still be hit. Fixes: 232ed8980217dd "i965/fs: Register allocator shoudn't use grf127..." Reviewed-by: Jose Maria Casanova Crespo <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* intel/fs: Properly handle 64-bit types in LOAD_PAYLOADJason Ekstrand2019-02-012-2/+7
| | | | | | | | | By just assigning dst.type to src[i].type, we ensure that the offset at the end of the loop actually offsets it by the right number of registers. Otherwise, we'll get into a case where we copy with a Q type and then offset with a D type and things get out of sync. Reviewed-by: Kenneth Graunke <[email protected]>
* intel/fs/cse: Split create_copy_instr into three casesJason Ekstrand2019-02-011-17/+17
| | | | | | | | | | Previously, we tried to combine all cases where the instruction being CSE'd writes to more than one MOV worth of registers into one case with a bit of special casing for LOAD_PAYLOAD. This commit splits things so that LOAD_PAYLOAD is entirely it's own case. This makes tweaking the LOAD_PAYLOAD case simpler in the next commit. Reviewed-by: Kenneth Graunke <[email protected]>
* intel/nir: Add global support to lower_mem_access_bit_sizesJason Ekstrand2019-02-011-0/+2
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* intel/fs: Fix memory corruption when compiling a CSOscar Blumberg2019-02-011-1/+2
| | | | | | | | Missing check for shader stage in the fs_visitor would corrupt the cs_prog_data.push information and trigger crashes / corruption later when uploading the CS state. Reviewed-by: Kenneth Graunke <[email protected]>
* spirv: Support LocalSizeId and LocalSizeHintId execution modesJason Ekstrand2019-02-011-0/+8
| | | | Reviewed-by: Caio Marcelo de Oliveira Filho <[email protected]>
* spirv: Handle OpExecutionModeIdJason Ekstrand2019-02-011-1/+4
| | | | Reviewed-by: Caio Marcelo de Oliveira Filho <[email protected]>
* spirv: Handle constants and types before execution modesJason Ekstrand2019-02-011-4/+4
| | | | | | | | We already defer handling the actual execution modes until after we've created the shader. This just moves it a tiny bit further so we actually have constants and types and can handle OpExecutionModeId. Reviewed-by: Caio Marcelo de Oliveira Filho <[email protected]>
* spirv: Rework handling of spec constant workgroup size built-insJason Ekstrand2019-02-012-4/+14
| | | | | | | | | | | Instead of handling it as part of the handling of constant instructions, just stash the vtn_value when we see the decoration and handle it explicitly later. This will let us re-order handling of constant instructions without breaking the Vulkan SPIR-V requirement that decorating a specialization constant as the WorkgroupSize built-in overrides the workgroup size set as an execution mode. Reviewed-by: Caio Marcelo de Oliveira Filho <[email protected]>
* spirv: Replace vtn_constant_value with vtn_constant_uintJason Ekstrand2019-02-013-15/+23
| | | | | | | | The uint version is less typing, supports different bit sizes, and is probably a bit more safe because we're actually verifying that the SPIR-V value is an integer scalar constant. Reviewed-by: Caio Marcelo de Oliveira Filho <[email protected]>
* radv: fix buildSamuel Pitoiset2019-02-012-2/+2
| | | | | Fixes: 9b9ccee4d64 ("radv: take LDS into account for compute shader occupancy stats") Signed-off-by: Samuel Pitoiset <[email protected]>
* radv: take LDS into account for compute shader occupancy statsTimothy Arceri2019-02-013-5/+14
| | | | | | Ported from d205faeb6c96. Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* ac/radv/radeonsi: add ac_get_num_physical_sgprs() helperTimothy Arceri2019-02-015-13/+12
| | | | Reviewed-by: Samuel Pitoiset <[email protected]>
* st/mesa: expose EXT_texture_compression_s3tc_srgbGurchetan Singh2019-02-011-0/+6
| | | | Reviewed-by: Erik Faye-Lund <[email protected]>
* i965: Set flag for EXT_texture_compression_s3tc_srgbGurchetan Singh2019-02-011-0/+1
| | | | Reviewed-by: Tapani Pälli <[email protected]>
* mesa/main: Expose EXT_texture_compression_s3tc_srgbGurchetan Singh2019-02-013-1/+4
| | | | | | | | | | Required for the following test: bin/compressedteximage GL_COMPRESSED_SRGB_ALPHA_S3TC_DXT1_EXT pass when emulating GL on GLES. Reviewed-by: Erik Faye-Lund <[email protected]>
* st/glsl_to_nir: remove dead local variablesTimothy Arceri2019-02-011-0/+3
| | | | | | | | | | | | | | Without this we do not end up with a deterministic NIR because temporary register variables are added in random order. NIR must be deterministic because we use it to produce a sha for the radeonsi backends disk cache. This fixes the shader cache for a bunch of shaders. Another positive is that this results in a large reduction in the size of the NIR that the state tracker stores to the disk cache. Reviewed-by: Kenneth Graunke <[email protected]>
* meson: remove -std=c++11 from intel/toolsDylan Baker2019-01-311-1/+1
| | | | | | | | | | | | | | | | | | | | for meson all C++ code is already compiled as C++11, so it's unnecessary. It's also the wrong way to do this, if we really needed this the correct way is to set: ```meson executable( ... override_options : ['cpp_std=c++11'], ) ``` Which ensures not only that the correct syntax for the current compiler is used, but also that meson doesn't create arguments like `-std=c++14 ... -std=c++11` Reviewed-by: Caio Marcelo de Oliveira Filho <[email protected]> Reviewed-by: Eric Engestrom <[email protected]>
* meson: fix style in intel/toolsDylan Baker2019-01-311-15/+17
| | | | | | | | | The `:` in options should always have one space before and after `foo : bar`, and lists do not get spaces around the braces: `[foo]` not `[ foo ]` Reviewed-by: Caio Marcelo de Oliveira Filho <[email protected]> Reviewed-by: Eric Engestrom <[email protected]>
* meson: remove build_by_default : trueDylan Baker2019-01-311-7/+0
| | | | | | | | | Which is and has always been the default. This is largely an artifact of how the building of these tools was controlled when the meson build was originally created. Reviewed-by: Caio Marcelo de Oliveira Filho <[email protected]> Reviewed-by: Eric Engestrom <[email protected]>
* st/mesa: Fix topogun-1.06-orc-84k-resize.trace crashNeha Bhende2019-01-311-0/+4
| | | | | | | | | | | | | We need to initialize all fields in rs->prim explicitly while creating new rastpos stage. Fixes: bac8534267 ("st/mesa: allow glDrawElements to work with GL_SELECT feedback") v2: Initializing all fields in rs->prim as per Ilia. Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* android,autotools,i965: Fix location of float64_glsl.hDylan Baker2019-01-313-2/+4
| | | | | | | | | | | | Android.mk and autotools disagree about where generated files should go, which wasn't a problem until we wanted to build a dist tarball. This corrects the problem by changing the output and include paths to be the same on android and autotools (meson already has the correct include path). Fixes: 7d7b30835cfb9eb89beca9fb8593d0954f79b84d ("automake: Fix path to generated source") Reviewed-by: Tapani Pälli <[email protected]>
* gallium: allow more PIPE_RESOURCE_ driver flagsMarek Olšák2019-01-311-1/+1
| | | | | | radeonsi has 8 and will probably have 9 soon. Reviewed-by: Roland Scheidegger <[email protected]>
* v3d: Fix image_load_store clamping of signed integer stores.Eric Anholt2019-01-311-1/+1
| | | | | | | | This was copy-and-paste fail, that oddly showed up in the CTS's reinterprets of r32f, rgba8, and srgba8 to rgba8i, but not r32ui and r32i to rgba8i or reinterprets to other signed int formats. Fixes: 6281f26f064a ("v3d: Add support for shader_image_load_store.")
* mesa: Skip partial InvalidateFramebuffer of packed depth/stencil.Eric Anholt2019-01-311-0/+23
| | | | | | | | | One of the CTS cases tries to invalidate just stencil of packed depth/stencil, and we incorrectly lost the depth contents. Fixes dEQP-GLES3.functional.fbo.invalidate.whole.unbind_read_stencil Fixes: 0c42b5f3cb90 ("mesa: wire up InvalidateFramebuffer") Reviewed-by: Marek Olšák <[email protected]>
* freedreno: more fixing release tarballRob Clark2019-01-311-1/+3
| | | | | Fixes: aa0fed10d35 freedreno: move ir3 to common location Signed-off-by: Rob Clark <[email protected]>
* freedreno: fix release tarballRob Clark2019-01-311-0/+1
| | | | | | Fixes: b4476138d5a freedreno: move drm to common location Reviewed-by: Eric Engestrom <[email protected]> Signed-off-by: Rob Clark <[email protected]>
* virgl: ARB_query_buffer_object supportDave Airlie2019-01-317-1/+58
| | | | | | v1.1: fix size define. Reviewed-by: Gurchetan Singh <[email protected]>
* virgl: enable elapsed time queriesDave Airlie2019-01-311-1/+1
| | | | | | GL underneath always has GL_TIME_ELAPSED so always enable these. Reviewed-by: Gurchetan Singh <[email protected]>
* radeonsi: fix a comment typo in si_fine_fence_setMarek Olšák2019-01-301-1/+1
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