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* nir: Implement optional b2f->iand loweringAlyssa Rosenzweig2018-05-182-1/+7
| | | | | | | | | | | | | | | | | | This pass is required by the Midgard compiler; our instruction set uses NIR-style booleans (~0 for true) but lacks a dedicated b2f instruction. Normally, this lowering pass would be implemented in a backend-specific algebraic pass, but this conflicts with the existing iand->b2f pass in nir_opt_algebraic.py, hanging the compiler. This patch thus makes the existing pass optional (default on -- all other backends should remain unaffected), adding an optional pass for lowering the opposite direction. v2: Defer lowering until late algebraic optimisations to allow optimising the b2f instruction itself. Signed-off-by: Alyssa Rosenzweig <[email protected]> Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Christian Gmeiner <[email protected]>
* radeonsi: skip ES output stores for undefined output componentsMarek Olšák2018-05-181-0/+3
| | | | | Tested-by: Dieter Nützel <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]>
* i965: isl: Move the MCS gen7+ assertion into ISLNanley Chery2018-05-182-2/+2
| | | | | | | This is useful for every user of ISL. Drop the comment along the way to match similar functions in ISL. Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/miptree: Remove format assertion in alloc_auxNanley Chery2018-05-181-5/+0
| | | | | | | | | intel_miptree_supports_{ccs,mcs,hiz} ensures the format is valid for the color or depth miptree before the miptree is assigned an aux_usage. alloc_aux switches on the aux_usage so don't assert that the format is valid. Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/miptree: Simplify the switch in supports_ccsNanley Chery2018-05-181-5/+1
| | | | | Reviewed-by: Topi Pohjolainen <[email protected]> Reviewed-by: Tapani Pälli <[email protected]>
* i965: Make get_ccs_surf succeed in alloc_auxNanley Chery2018-05-182-10/+11
| | | | | | | | | | Synchronize the requirements listed in isl_surf_get_ccs_surf with intel_miptree_supports_ccs by importing a restriction from ISL. Some implications: * We successfully create every aux_surf in alloc_aux * We only return false from alloc_aux if we run out of memory Reviewed-by: Topi Pohjolainen <[email protected]>
* llvmpipe: fix check for a no-op shaderBrian Paul2018-05-181-2/+4
| | | | | | | | | | The tgsi_info.num_tokens fix broke llvmpipe's detection of no-op shaders. Fix the code to check for num_instructions <= 1 instead. Fixes: 8fde9429c36b75 ("tgsi: fix incorrect tgsi_shader_info::num_tokens computation") Tested-by: Roland Scheidegger <[email protected]> Reviewed-by: Roland Scheidegger <[email protected]>
* radv: pass radv_nir_compiler_options directly to create_llvm_function()Samuel Pitoiset2018-05-181-4/+3
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Timothy Arceri <[email protected]>
* st/mesa: only define GLSL 1.4 for compat if driver supports itChristian Gmeiner2018-05-181-1/+1
| | | | | | | | | | | | | Currently GLSL 1.4 is defined for all gallium drivers even only GLSL 1.2 is supported as seen on etnaviv. v1 -> v2: - use _min(..) as suggested by Lucas Stach and Michel Dänzer Fixes: 4560aad780b ("mesa: add GLSLVersionCompat constant") Signed-off-by: Christian Gmeiner <[email protected]> Reviewed-by: Lucas Stach <[email protected]> Reviewed-by: Timothy Arceri <[email protected]>
* vbo: remove MaxVertexAttribStride assert check.Dave Airlie2018-05-181-1/+0
| | | | | | | | Some drivers (virgl) don't support GL4.4 or GLES3.1 yet, so never fill in this const. Reviewed-by: Mathias Fröhlich <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* mesa: drop GL_EXT_polygon_offset supportTimothy Arceri2018-05-188-36/+0
| | | | | | | | glPolygonOffset() has been part of the GL standard since 1.1. Also niether AMD or Nvidia support this in their binary drivers. Reviewed-by: Marek Olšák <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=61761
* tgsi: fix incorrect tgsi_shader_info::num_tokens computationBrian Paul2018-05-171-2/+1
| | | | | | | | | | | | | We were incrementing num_tokens in each loop iteration while parsing the shader. But each call to tgsi_parse_token() can consume more than one token (and often does). Instead, just call the tgsi_num_tokens() function. Luckily, this issue doesn't seem to effect any current users of this field (llvmpipe just checks for <= 1, for example). Reviewed-by: Neha Bhende<[email protected]> Reviewed-by: Roland Scheidegger <[email protected]>
* radv: add radv_emit_shader_pointer() helperSamuel Pitoiset2018-05-173-13/+18
| | | | | | | For future work (support for 32-bit GPU pointers). Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: add some helpers for cleaning up radv_get_preamble_cs()Samuel Pitoiset2018-05-171-86/+128
| | | | | | | Because this function looks a bit ugly to me. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* amd: remove support for LLVM 4.0Marek Olšák2018-05-1710-223/+113
| | | | | | | It doesn't support GFX9. Acked-by: Dave Airlie <[email protected]> Acked-by: Samuel Pitoiset <[email protected]>
* mesa: The glArrayElement api is independent of the current program.Mathias Fröhlich2018-05-172-2/+2
| | | | | | | | | All the shader program dependent handling is done on the level of the gl_Context::Array._DrawVAO/_DrawVAOEnabledAttribs. So, skip array element invalidation on _NEW_PROGRAM. Reviewed-by: Brian Paul <[email protected]> Signed-off-by: Mathias Fröhlich <[email protected]>
* mesa: Flag _NEW_ARRAY only if we are changing ctx->Array.VAO.Mathias Fröhlich2018-05-171-6/+14
| | | | | | | | | For the VAO internal helper functions that may be called with a non current VAO, flag the _NEW_ARRAY state only if it is the current ctx->Array.VAO. Reviewed-by: Brian Paul <[email protected]> Signed-off-by: Mathias Fröhlich <[email protected]>
* mesa: Remove flush_vertices argument from VAO methods.Mathias Fröhlich2018-05-179-57/+51
| | | | | | | The flush_vertices argument is now unused, remove it. Reviewed-by: Brian Paul <[email protected]> Signed-off-by: Mathias Fröhlich <[email protected]>
* mesa: Remove FLUSH_VERTICES from VAO state changes.Mathias Fröhlich2018-05-171-59/+6
| | | | | | | | | Pending draw calls on immediate mode or display list calls do not depend on changes of the VAO state. So, remove calls to FLUSH_VERTICES and flag _NEW_ARRAY as appropriate. Reviewed-by: Brian Paul <[email protected]> Signed-off-by: Mathias Fröhlich <[email protected]>
* swr/rast: Added FEClipRectangles eventAlok Hota2018-05-172-0/+4
| | | | | | and also added some comments Reviewed-By: George Kyriazis <[email protected]>
* swr/rast: Whitespace and tab-to-spaces changesAlok Hota2018-05-175-17/+18
| | | | Reviewed-By: George Kyriazis <[email protected]>
* swr/rast: fix VCVTPD2PS generation for AVX512Alok Hota2018-05-171-2/+10
| | | | Reviewed-By: George Kyriazis <[email protected]>
* swr/rast: Rectlist support for GSAlok Hota2018-05-176-1/+102
| | | | | | | Add rectlist as an option for GS. Needed to support some driver optimizations. Reviewed-By: George Kyriazis <[email protected]>
* swr/rast: Remove unneeded virtual from methodsAlok Hota2018-05-171-2/+2
| | | | Reviewed-By: George Kyriazis <[email protected]>
* broadcom/vc4: Native fence fd supportStefan Schake2018-05-176-11/+107
| | | | | | | | | | | | | | | With the syncobj support in place, lets use it to implement the EGL_ANDROID_native_fence_sync extension. This mostly follows previous implementations in freedreno and etnaviv. v2: Drop the flags (Eric) Handle in_fence_fd already in job_submit (Eric) Drop extra vc4_fence_context_init (Eric) Dup fds with CLOEXEC (Eric) Mention exact extension name (Eric) Signed-off-by: Stefan Schake <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* broadcom/vc4: Store job fence in syncobjStefan Schake2018-05-173-4/+35
| | | | | | | | | This gives us access to the fence created for the render job. v2: Drop flag (Eric) Signed-off-by: Stefan Schake <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* broadcom/vc4: Detect syncobj supportStefan Schake2018-05-172-0/+7
| | | | | | | | | | We need to know if the kernel supports syncobj submission since otherwise all the DRM syncobj calls fail. v2: Use drmGetCap to detect syncobj support (Eric) Signed-off-by: Stefan Schake <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* v3d: Add support for glSampleMask / glSampleCoverage.Eric Anholt2018-05-177-5/+36
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* v3d: Enable NaN propagation in the VS and CS as well.Eric Anholt2018-05-174-4/+12
| | | | Fixes piglit vs-isnan-*.shader_test at the expense of gl-1.0-spot-light.
* i965/blorp: Disable BLORP clear color updatesNanley Chery2018-05-171-2/+4
| | | | | | | With the previous patches, we now update the indirect clear color buffer every time the clear color changes. Avoid redundant updates. Reviewed-by: Jason Ekstrand <[email protected]>
* intel/blorp: Add a NO_UPDATE_CLEAR_COLOR batch flagNanley Chery2018-05-172-2/+9
| | | | | | | | | Allow callers to handle updating the indirect clear color buffer themselves. This can reduce the number of clear color updates in the case where a caller performs multiple fast clears with the same clear color. Reviewed-by: Jason Ekstrand <[email protected]>
* i965/blorp: Also skip the fast clear if the clear color differsNanley Chery2018-05-171-4/+3
| | | | | | | | If the aux state is CLEAR and clear color value has changed, only the surface state must be updated. The bit-pattern in the aux buffer is exactly the same. Reviewed-by: Jason Ekstrand <[email protected]>
* i965/clear: Drop a stale comment in fast_clear_depthNanley Chery2018-05-171-4/+0
| | | | | | | | | This comment made more sense when it was above the calls to intel_miptree_slice_set_needs_depth_resolve(). We stopped using these functions at commit 554f7d6d02931ea45653c8872565d21c1678a6da ("i965: Move depth to the new resolve functions"). Reviewed-by: Jason Ekstrand <[email protected]>
* i965: Update the indirect buffer in set_clear_colorNanley Chery2018-05-172-37/+13
| | | | | | | | | | | | | | | | | | | | | For depth buffers, we avoid fast-clearing if the aux_state is already CLEAR. We do the same for color buffers only if the clear color doesn't change. We require that the clear colors match because, in that case, we don't update the indirect clear color outside of BLORP. Update the indirect clear color for color buffers as well. We'll enable the same depth buffer optimization for color buffers in a later patch. Note that we're now actually updating the indirect clear color twice in the case where we use BLORP to perform the fast-clear. This is only temporary. In later patches, we'll prevent BLORP from performing the update. v2: Add more context to the commit message (Topi). Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/clear: Remove an early return in fast_clear_depthNanley Chery2018-05-171-5/+0
| | | | | | | | | | | Reduce complexity and allow the next patch to delete some code. With this change, clear operations will still be skipped and setting the aux_state will cause no side-effects. Remove the associated comment which implies an early return. Reviewed-by: Rafael Antognolli <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* i965: Use set_clear_color for depth miptreesNanley Chery2018-05-173-19/+2
| | | | | | | Reduce code duplication now and prevent it in the following commits. Reviewed-by: Topi Pohjolainen <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* Revert "i965: Make the miptree clear color setter take a gl_color_union"Nanley Chery2018-05-173-7/+6
| | | | | | | | | | | | This reverts commit 1d94aa19877fb702ffacacde28ad7253cce72c97. The next patch will make depth miptrees use the clear color setter that was originally being used for color miptrees. Go back to using the isl_color_value parameter because it's the same type as the fast_clear_color field used by color and depth miptrees. Reviewed-by: Topi Pohjolainen <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* i965/miptree: Unify aux buffer allocationNanley Chery2018-05-172-142/+82
| | | | | | | | | | There isn't much that changes between the aux allocation functions. Remove the duplicated code. v2: Inline the switch statement (Jason). Reviewed-by: Topi Pohjolainen <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* i965: Prepare to delete intel_miptree_alloc_ccs()Nanley Chery2018-05-173-15/+16
| | | | | | | | | | | | We're going to delete intel_miptree_alloc_ccs() in the next commit. With that in mind, replace the use of this function in do_single_blorp_clear() with intel_miptree_alloc_aux() and move the delayed allocation logic to it's callers. v2: Duplicate the delayed allocation comment (Topi Pohjolainen). Reviewed-by: Topi Pohjolainen <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* i965/miptree: Drop the mt param from alloc_aux_bufferNanley Chery2018-05-171-5/+4
| | | | | | Drop an unused parameter. Reviewed-by: Jason Ekstrand <[email protected]>
* i965/miptree: Drop the alloc_flags param from alloc_aux_bufferNanley Chery2018-05-171-15/+14
| | | | | | | We have enough information to determine the optimal flags internally. Reviewed-by: Topi Pohjolainen <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* i965/miptree: Drop the name param from alloc_aux_bufferNanley Chery2018-05-171-5/+4
| | | | | | A name of "aux-miptree" should be sufficient. Reviewed-by: Jason Ekstrand <[email protected]>
* i965/miptree: Initialize the indirect clear color to zeroNanley Chery2018-05-171-11/+22
| | | | | | | | | | | | | | | | | | | | | | | | The indirect clear color isn't correctly tracked in intel_miptree::fast_clear_color. The initial value of ::fast_clear_color is zero, while that of the indirect clear color is undefined. Topi Pohjolainen discovered this issue with MCS buffers. This issue is apparent when fast-clearing an MCS buffer for the first time with glClearColor = {0.0,}. Although the indirect clear color is undefined, the initial aux state of the MCS is CLEAR and the tracked clear color is zero, so we avoid updating the indirect clear color with {0.0,}. Make the indirect clear color match the initial value of ::fast_clear_color. Note: although we only have to drop HiZ's BO_ALLOC_BUSY flag for gen10+, we also drop it pre-gen10 to keep things simple. We add this flag back for pre-gen10 in a later patch. v2: Add a note about dropping HiZ's BO_ALLOC_BUSY flag (Topi). Reviewed-by: Topi Pohjolainen <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* i965/miptree: Add and use a memset option in alloc_aux_bufferNanley Chery2018-05-171-37/+31
| | | | | | | | Add infrastructure for initializing the clear color BO. intel_miptree_init_mcs is no longer needed with change. Reviewed-by: Topi Pohjolainen <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* i965/miptree: Zero-initialize CCS_D buffersNanley Chery2018-05-171-6/+4
| | | | | | | | | | | | | | | | | | Before this patch, the aux_state was actually AUX_INVALID because the BO was never defined. This was fine on single slice miptrees because we would fast-clear the resource right after creation. For multi-slice miptrees on SKL+ however, this results in undefined behavior when accessing a non-base slice. Here's a specific example: 1) Fast clear level 0 * Undefined CCS_D buffer allocated in "PASS_THROUGH" state. * Level 0 transitions to the CLEAR state. 2) Render to level 1 * Level 1 may have a 2-bit pattern of 2's. * Rendering with a 2 in the CCS is undefined. Cc: <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* i965/miptree: Fix handling of uninitialized MCS buffersNanley Chery2018-05-171-7/+7
| | | | | | | | | | | | | Before this patch, if we failed to initialize an MCS buffer, we'd end up in a state in which the miptree thinks it has an MCS buffer, but doesn't. We also leaked the clear_color_bo if it existed. With this patch, we now free the miptree aux buffer resources and let intel_miptree_alloc_mcs() know that the MCS buffer no longer exists. Cc: <[email protected]> Reviewed-by: Tapani Pälli <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* radv: only declare the ESGS rings for pre GFX9 chipsSamuel Pitoiset2018-05-171-4/+10
| | | | | | | GFX9 uses LDS instead. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: allow to print GPU info with RADV_DEBUG=infoSamuel Pitoiset2018-05-172-0/+5
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: do not emit unnecessary ES output storesSamuel Pitoiset2018-05-171-3/+23
| | | | | | | | | | | | | | | | | | | | | | GFX9: Totals from affected shaders: SGPRS: 472 -> 464 (-1.69 %) VGPRS: 576 -> 584 (1.39 %) Code Size: 45432 -> 44324 (-2.44 %) bytes Max Waves: 40 -> 40 (0.00 %) VI: SGPRS: 720 -> 720 (0.00 %) VGPRS: 728 -> 728 (0.00 %) Code Size: 45348 -> 43992 (-2.99 %) bytes Max Waves: 120 -> 120 (0.00 %) This affects Rise of Tomb Raider and the three Vulkan demos that use a geometry shader (geometryshader, deferredshadows and viewportarray). Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: do not emit unnecessary GS output storesSamuel Pitoiset2018-05-171-0/+7
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
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