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* gallium/radeon: set GTT WC on tiled texturesMarek Olšák2016-04-121-1/+2
| | | | | | | | Just for consistency. This should have no effect, because OpenGL textures always go to VRAM. Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Edward O'Callaghan <[email protected]>
* gallium/radeon: relax requirements on VRAM placements on APUsMarek Olšák2016-04-124-0/+37
| | | | | | | This makes Tonga with vramlimit=128 2x faster in Heaven. Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Edward O'Callaghan <[email protected]>
* winsys/amdgpu: remove hack for low VRAM configurationMarek Olšák2016-04-121-10/+0
| | | | | | | A better solution will be used. Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Edward O'Callaghan <[email protected]>
* r600g: disable aniso filtering for non-mipmap textures on EGMarek Olšák2016-04-121-1/+3
| | | | | | this is the default behavior of the closed driver when running on VI Reviewed-by: Nicolai Hähnle <[email protected]>
* r600g: clean up aniso state translationMarek Olšák2016-04-126-31/+29
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: disable aniso filtering for non-mipmap textures on SI-CIMarek Olšák2016-04-122-1/+45
| | | | | | | | | The closed driver does this, but it looks at base_level and last_level and uses a conditional assignment, which LLVM can't generate on SGPRs. That led me to invent this solution that abuses the image descriptor. Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: clean up aniso state translationMarek Olšák2016-04-123-15/+23
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: enable some sampler fields to match the closed driverMarek Olšák2016-04-122-2/+10
| | | | | | copied from the Vulkan driver Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium/radeon: fix maximum texture anisotropy setupMarek Olšák2016-04-121-5/+9
| | | | | | We were overdoing it for non-power-of-two values. Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium/radeon: never choose a linear tiling for DB surfacesMarek Olšák2016-04-121-7/+6
| | | | | | | Just for consistency. This is actually not a problem, because both addrlib and radeon check and fix this. Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium/radeon: removing dead code for sharing stencil buffersMarek Olšák2016-04-121-4/+0
| | | | | | | This is a remnant of the times when the DDX was allocating depth-stencil buffers for windows. Now, st/dri allocates them and doesn't share them. Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: allow clearing buffers >= 4 GBMarek Olšák2016-04-124-7/+7
| | | | | | | Only CMASK and DCC clears can use this, because only textures can be so large. Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium/radeon: allow allocating textures >= 4 GBMarek Olšák2016-04-123-14/+17
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* winsys/radeon: fix printing allocation failuresMarek Olšák2016-04-121-4/+4
| | | | | | print as unsigned instead of signed Reviewed-by: Nicolai Hähnle <[email protected]>
* winsys/amdgpu: add support for 64-bit buffer sizesMarek Olšák2016-04-125-19/+30
| | | | | | v2: fail in radeon_winsys_bo_create if size > 32 bits Reviewed-by: Nicolai Hähnle <[email protected]>
* pb_buffer: switch pb_buffer::size to 64 bitsMarek Olšák2016-04-128-16/+21
| | | | | | being able to allocate more than 4 GB may be useful Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium/radeon: remove R600_QUERY_HW_FLAG_TIMERMarek Olšák2016-04-124-7/+3
| | | | | | | not used anymore Reviewed-by: Edward O'Callaghan <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium/radeon: merge timer and non-timer query listsMarek Olšák2016-04-124-82/+23
| | | | | | | All of them are paused only between IBs. Reviewed-by: Edward O'Callaghan <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* r600g: don't manually stop queries for blitterMarek Olšák2016-04-121-3/+0
| | | | | | | r600_set_active_query_state does it better. Reviewed-by: Edward O'Callaghan <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* r600g: add pausing pipeline & streamout queries into set_active_query_stateMarek Olšák2016-04-125-1/+38
| | | | | Reviewed-by: Edward O'Callaghan <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* r600g: implement set_active_query_state for pausing occlusion queriesMarek Olšák2016-04-127-9/+24
| | | | | | | Use ZPASS_INCREMENT_DISABLE everywhere. Reviewed-by: Edward O'Callaghan <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* r600g: simplify r600_set_occlusion_query_stateMarek Olšák2016-04-124-7/+3
| | | | | | | The caller does the same checking. Reviewed-by: Edward O'Callaghan <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium/radeon: move pipeline stat context flags to common codeMarek Olšák2016-04-124-10/+10
| | | | | Reviewed-by: Edward O'Callaghan <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* r600g: fix typo in r600 register definitionsMarek Olšák2016-04-121-1/+1
| | | | Acked-by: Edward O'Callaghan <[email protected]>
* gallium/radeon: unify checking streamout enable stateMarek Olšák2016-04-124-11/+9
| | | | | Reviewed-by: Edward O'Callaghan <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: fix mask checking when emitting scissors and viewportsMarek Olšák2016-04-121-4/+8
| | | | | Reviewed-by: Nicolai Hähnle <[email protected]> Reviewed-by: Grigori Goronzy <[email protected]>
* radeonsi: implement and rely on set_active_query_stateMarek Olšák2016-04-124-4/+45
| | | | | Reviewed-by: Edward O'Callaghan <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium: pause queries for all meta opsMarek Olšák2016-04-128-0/+14
| | | | | Reviewed-by: Roland Scheidegger <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium: add pipe_context::set_active_query_state for pausing queriesMarek Olšák2016-04-1220-0/+142
| | | | | Reviewed-by: Roland Scheidegger <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: Synchronize a streamout write after read hazard.Bas Nieuwenhuizen2016-04-121-0/+6
| | | | | | Signed-off-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* nv30: Add missing PIPE_SHADER_CAP_INTEGERS to get_shader_param()Hans de Goede2016-04-121-0/+1
| | | | | | | | Add missing PIPE_SHADER_CAP_INTEGERS for frag shaders to nv30_screen_get_shader_param(). Signed-off-by: Hans de Goede <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]>
* dri/i965: extend GLES3 sRGB workaround to cover all formatsHaixia Shi2016-04-121-4/+3
| | | | | | | | | | It is incorrect to assume BGRA byte order for the GLES3 sRGB workaround. v2: use _mesa_get_srgb_format_linear to handle all formats Signed-off-by: Haixia Shi <[email protected]> Reviewed-by: Stéphane Marchesin <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Add autogenerated 'brw_nir_trig_workarounds.c' to gitignoreEduardo Lima Mitev2016-04-121-0/+1
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* glsl: Update hash table comments in constant propagationRhys Kidd2016-04-121-3/+3
| | | | | Signed-off-by: Rhys Kidd <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* softpipe: add SSBO/shader atomics support.Dave Airlie2016-04-1211-6/+466
| | | | | | | | | | This adds support for the features requires for ARB_shader_storage_buffer_object and ARB_shader_atomic_counters, ARB_shader_atomic_counter_ops. [airlied: some cleanups applied] Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Roland Scheidegger <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* draw: add support for passing buffers to vs/gs shaders.Dave Airlie2016-04-125-3/+32
| | | | | | | | Like the image code, but for shader buffers this time. Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Roland Scheidegger <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* tgsi: add support for buffer/atomic operations to tgsi_exec.Dave Airlie2016-04-125-14/+245
| | | | | | | | | This adds support for doing load/store/atomic operations on buffer objects. Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Roland Scheidegger <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* tgsi: set nonhelpermask for vertex shadersDave Airlie2016-04-121-0/+1
| | | | | | | | | | | For atomic operations we really need to avoid executing unnecessary shaders, so for some tests that just draw a single point we only want one vertex to get processed not 4, this fixes a number of the atomic counters tests. Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Roland Scheidegger <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* nir: Fix typo in commentIan Romanick2016-04-111-1/+1
| | | | | | Trivial. Signed-off-by: Ian Romanick <[email protected]>
* nir: Merge redudant integer clamping.Markus Wick2016-04-111-1/+4
| | | | | | | | | Dolphin uses them a lot. Range tracking would be better in the long term, but this two lines works fine for now. Signed-off-by: Markus Wick <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* i965: Port INTEL_PRECISE_TRIG=1 to NIR.Kenneth Graunke2016-04-117-28/+58
| | | | | | | | | | | | | | | | | | | | This makes the extra multiply visible to NIR's algebraic optimizations (for constant reassociation) as well as constant folding. This means that when the result of sin/cos are multiplied by an constant, we can eliminate the extra multiply altogether, reducing the cost of the workaround. It also means we only have to implement it one place, rather than in both backends. This makes INTEL_PRECISE_TRIG=1 cost nothing on GPUTest/Volplosion, which has a ton of sin() calls, but always multiplies them by an immediate constant. The extra multiply gets folded away. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eduardo Lima Mitev <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965: Pass brw_compiler into brw_preprocess_nir() instead of is_scalar.Kenneth Graunke2016-04-112-3/+6
| | | | | | | | | | I want to be able to read other fields. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Alejandro Piñeiro <[email protected]> Reviewed-by: Eduardo Lima Mitev <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* nir: Silence unused "options" warning in algebraic passes.Kenneth Graunke2016-04-111-0/+1
| | | | | | | | | | | Some passes may not refer to options->..., at which point the compiler will warn about an unused variable. Just cast to void unconditionally to shut it up. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eduardo Lima Mitev <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* nir: Do basic constant reassociation.Kenneth Graunke2016-04-111-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Many shaders contain expression trees of the form: const_1 * (value * const_2) Reorganizing these to (const_1 * const_2) * value will allow constant folding to combine the constants. Sometimes, these constants are 2 and 0.5, so we can remove a multiply altogether. Other times, it can create more immediate constants, which can actually hurt. Finding a good balance here is tricky. While much more could be done, this simple patch seems to have a lot of positive benefit while having a low downside. shader-db results on Broadwell: total instructions in shared programs: 8963768 -> 8961369 (-0.03%) instructions in affected programs: 438318 -> 435919 (-0.55%) helped: 1502 HURT: 245 total cycles in shared programs: 71527354 -> 71421516 (-0.15%) cycles in affected programs: 11541788 -> 11435950 (-0.92%) helped: 3445 HURT: 1224 Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eduardo Lima Mitev <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* radeon/uvd: alignment fix for decode message bufferBoyuan Zhang2016-04-111-1/+1
| | | | | Signed-off-by: Boyuan Zhang <[email protected]> Reviewed-by: Christian König <[email protected]>
* st/mesa: replace _mesa_sysval_to_semantic table with functionBrian Paul2016-04-113-68/+69
| | | | | | | | | | Instead of using an array indexed by SYSTEM_VALUE_x, just use a switch statement. This fixes a regression caused by inserting new SYSTEM_VALUE_ enums but not updating the mapping to TGSI semantics. v2: fix a few switch statement mistakes for compute-related enums Reviewed-by: Ilia Mirkin <[email protected]>
* nir/lower_system_values: Add support for several computed valuesJason Ekstrand2016-04-114-4/+76
| | | | Reviewed-by: Rob Clark <[email protected]>
* glsl/shader_enums: Add the other two compute builtinsJason Ekstrand2016-04-112-0/+4
| | | | | | | | These weren't added before because they are actually calculated values that are computed from other inputs. However, in order to handle them in nir_lower_system_values, it's nice for them to have a cannonical locaiton. Reviewed-by: Rob Clark <[email protected]>
* glsl/shader_enums: Add an enum for Vulkan InstanceIndexJason Ekstrand2016-04-112-0/+8
| | | | | | | In Vulkan, you have InstanceIndex which begins at the base instance value rather than the zero-based InstanceID of GL. Reviewed-by: Rob Clark <[email protected]>
* mesa: add missing header to the tarballEmil Velikov2016-04-111-0/+1
| | | | Signed-off-by: Emil Velikov <[email protected]>
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