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* radv: use a 16 bytes array for the sampled/storage image descriptorsSamuel Pitoiset2017-11-203-12/+8
| | | | | | | This allows to update them with only one memcpy(). Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* radv: do not add the query pool BO to the list in vkCmdEndQuery()Samuel Pitoiset2017-11-201-1/+3
| | | | | | | | | As per the spec, the query identified by queryPool and query must currently be active. Applications have to call vkCmdBeginQuery() before, and thus the query pool BO will already be in the list. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* radv: only load needed depth clear regs for fast depth clearsSamuel Pitoiset2017-11-201-2/+12
| | | | | | | | | Similar to how the driver sets the depth clear regs after a fast depth clear. Most of the time, this will copy a 32-bit reg instead of a 64-bit reg. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: do not add the image BO in radv_set_depth_clear_regs()Samuel Pitoiset2017-11-201-2/+0
| | | | | | | | | | For the fast path, radv_fill_buffer() ensures that the BO is already in the list. For the slow path, the depth surface is part of the framebuffer which means the BO is added to the list when the framebuffer is emitted. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: remove useless assertion in emit_depthstencil_clear()Samuel Pitoiset2017-11-201-4/+0
| | | | | | | Already checked in emit_clear(). Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: remove useless check in radv_set_depth_clear_regs()Samuel Pitoiset2017-11-201-1/+1
| | | | | | | | aspects can't be zero and there is an assertion that ensures it's not in emit_clear(). Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* glsl: Catch subscripted calls to undeclared subroutinesGeorge Barrett2017-11-201-2/+7
| | | | | | | | | | generate_array_index fails to check whether the target of a subroutine call exists in the AST, potentially passing around null ir_rvalue pointers eventuating in abort/segfault. Fixes: fd01840c0bd3 ("glsl: add AoA support to subroutines") Reviewed-by: Timothy Arceri <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=100438
* broadcom/vc5: Fix up integer texture handling.Eric Anholt2017-11-192-27/+51
| | | | | | | | The original spec I had didn't expose integer textures and suggested that you use unfiltered floats. Now there are proper formats for them. Fixes 16- and 32-bit texwrap integer tests in piglit, and dEQP-GLES3.functional.fbo.completeness.renderable.renderbuffer.color0.rgb10_a2ui.
* broadcom/vc5: Fix simulator assertion failures about color RT clears.Eric Anholt2017-11-191-2/+19
| | | | | | | | When we tried to clear color while storing depth, it assertion failed about basically not having enough information to decide which color RT to clear. It turns out the STORE_GENERAL picks the buffer according to the color buffer being stored, or all of them if NONE. If you're doing depth, it doesn't know which to pick.
* freedreno/ir3: add texture gather supportRob Clark2017-11-182-2/+17
| | | | Signed-off-by: Rob Clark <[email protected]>
* etnaviv: enable full overwrite when no color buffer is presentLucas Stach2017-11-182-3/+3
| | | | | | | | The OVERWRITE bit disables destination fetches, which is exactly what we want when there is no valid color buffer bound. Signed-off-by: Lucas Stach <[email protected]> Reviewed-by: Wladimir J. van der Laan <[email protected]>
* i965: Stop including brw_cfg.h in brw_disasm_info.hJason Ekstrand2017-11-171-1/+5
| | | | | | | | | | | | The brw_disasm_info header is included by certain tools in order to get shader assembly from binaries so it's a semi-external header. Including brw_cfg.h also pulls in brw_shader.h so you end up getting quite a bit of our back-end compiler internals. Instead, make the couple of forward declarations we need and make the header more stand-alone. This fixes the meson build. Reviewed-by: Matt Turner <[email protected]> Fixes: 4f82b17287194ca7d10816f6cfe4712a3e0a03fc
* i965: Mark BOs as external when we export their handleJason Ekstrand2017-11-173-1/+11
| | | | | | | | | | | | | | | | | | | | Almost all of our BO export paths were already properly marked the BO as external and added it to the handle table. Most export use-cases go through a prime fd or flink where we have a brw_bo export helper that does the right thing. The one missing one happens when you call queryImage and ask for __DRI_IMAGE_ATTRIB_HANDLE. We just grabbed the gem handle out of the BO (because it's really easy to do that) and handed it off to the client; what could go wrong? As it turns out, this path is used by basically every compositor that wants to turn around and call drmModeAddFB2 on it so it can hand it off to display. The result, as of 4b1e70cc57d7ff5f465544644b2180dee1490cee, is that we no longer set MOCS_PTE on those surfaces and the kernel's attempts to disable caching fail and we scanout gets corruption. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103759 Fixes: 4b1e70cc57d7ff5f465544644b2180dee1490cee Reviewed-by: Kenneth Graunke <[email protected]> Cc: [email protected]
* i965/bufmgr: Add a helper to mark a BO as externalJason Ekstrand2017-11-171-6/+11
| | | | | Reviewed-by: Kenneth Graunke <[email protected]> Cc: [email protected]
* i965: Correct disasm_info usage in eu_validate testAndres Gomez2017-11-181-6/+6
| | | | | | | | Fixes: 4f82b1728719 ("i965: Rewrite disassembly annotation code") Cc: Matt Turner <[email protected]> Signed-off-by: Andres Gomez <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* broadcom/vc5: Set up the padded height at surface creation time.Eric Anholt2017-11-173-16/+15
| | | | | This centralizes the calculation in the surface, instead of in each load/store.
* broadcom/vc5: Ensure that there is always a TLB write.Eric Anholt2017-11-171-1/+17
| | | | | This should fix some GPU hangs in our (currently always single-threaded) fragment shaders, and definitely fixes assertion failures in simulation.
* broadcom/vc5: Fix clear color for swap_color_rb render targets.Eric Anholt2017-11-171-0/+9
| | | | Fixes dEQP-GLES3.functional.depth_stencil_clear.depth.*
* broadcom/vc5: Fix pasteo in front stencil ref value setup.Eric Anholt2017-11-171-1/+1
| | | | Fixes piglit masked-clear.
* broadcom/vc5: Fix colormasking when we need to swap r/b colors.Eric Anholt2017-11-171-9/+24
| | | | Fixes part of piglit masked-clear.
* broadcom/vc5: Enable the Z min/max clipping planes.Eric Anholt2017-11-171-2/+0
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* broadcom/vc5: Fix driver for new PIPE_SHADER_CAP_MAX_HW_ATOMIC_*.Eric Anholt2017-11-171-0/+2
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* r300: add PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER* switch casesBrian Paul2017-11-171-0/+2
| | | | | | To silence compiler warnings. Reviewed-by: Marek Olšák <[email protected]>
* tgsi: s/uint/enum pipe_shader_type/Brian Paul2017-11-172-2/+2
| | | | Roland Scheidegger <[email protected]>
* tgsi: bump tgsi_opcode_info::output_mode size to 4 bitsBrian Paul2017-11-172-1/+3
| | | | | | | To avoid problems with MSVC. And verify size with ASSERT_BITFIELD_SIZE(). Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Charmaine Lee <[email protected]>
* i965: Revert Gen8 aspect of VF PIPE_CONTROL workaround.Kenneth Graunke2017-11-171-1/+5
| | | | | | | This apparently causes hangs on Broadwell, so let's back it out for now. I think there are other PIPE_CONTROL workarounds that we're missing. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103787
* egl: Convert int to attrib in eglGetPlatformDisplayAdam Jackson2017-11-173-25/+25
| | | | | | | | ... because converting attrib to int truncates, and that's bad. Signed-off-by: Adam Jackson <[email protected]> Reviewed-by: Eric Engestrom <[email protected]> Reviewed-by: Emil Velikov <[email protected]>
* i965: Rename intel_asm_annotation -> brw_disasm_infoMatt Turner2017-11-176-8/+8
| | | | | | | It was the only file named intel_* in the compiler. Reviewed-by: Samuel Iglesias Gonsálvez <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Rewrite disassembly annotation codeMatt Turner2017-11-1711-171/+174
| | | | | | | | | | | | | | | The old code used an array to store each "instruction group" (the new, better name than the old overloaded "annotation"), and required a memmove() to shift elements over in the array when we needed to split a group so that we could add an error message. This was confusing and difficult to get right, not the least of which was because the array has a tail sentinel not included in .ann_count. Instead use a linked list, a data structure made for efficient insertion. Acked-by: Samuel Iglesias Gonsálvez <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Simplify annotation_insert_error()Matt Turner2017-11-171-9/+6
| | | | | Reviewed-by: Samuel Iglesias Gonsálvez <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Move common code out of #ifdefMatt Turner2017-11-172-9/+4
| | | | | | | | | I'm going to change the call in a later patch and with the difference in indentation level it wasn't immediately obvious that the calls were identical. Reviewed-by: Samuel Iglesias Gonsálvez <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Remove DWord length from MI_FLUSH_DW definitionAnuj Phogat2017-11-171-1/+1
| | | | | | | | Fixes: 6165fda59b8 ("i965: Program DWord Length in MI_FLUSH_DW") Cc: <[email protected]> Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Nanley Chery <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* anv/cmd_buffer: Take bo_offset into account in fast clear state addressesJason Ekstrand2017-11-171-1/+1
| | | | | | | | Otherwise, if the image is not bound to the start of the buffer, we're going to be reading and writing its fast clear state in the wrong spot. Reviewed-by: Lionel Landwerlin <[email protected]> Cc: [email protected]
* anv/cmd_buffer: Advance the address when initializing clear colorsJason Ekstrand2017-11-171-3/+6
| | | | | | | | Found by inspection Reviewed-by: Lionel Landwerlin <[email protected]> Reviewed-by: Nanley Chery <[email protected]> Cc: [email protected]
* radeon/video: enable encode support for ravenBoyuan Zhang2017-11-171-1/+2
| | | | | | | Enable h.264 encode for vcn hardware (raven) Signed-off-by: Boyuan Zhang <[email protected]> Acked-by: Christian König <[email protected]>
* radeonsi: enable vcn encodeBoyuan Zhang2017-11-171-1/+3
| | | | | | | Enable vcn encode by creating radeon_encoder for vcn. Signed-off-by: Boyuan Zhang <[email protected]> Acked-by: Christian König <[email protected]>
* radeon/vcn: add create encoderBoyuan Zhang2017-11-171-1/+81
| | | | | | | Add implementation for create_encoder interface for vcn encode. Signed-off-by: Boyuan Zhang <[email protected]> Acked-by: Christian König <[email protected]>
* radeon/vcn: add encode get feedbackBoyuan Zhang2017-11-171-1/+14
| | | | | | | Add implementation for get_feedback interface for vcn encode. Signed-off-by: Boyuan Zhang <[email protected]> Acked-by: Christian König <[email protected]>
* radeon/vcn: add encode destroyBoyuan Zhang2017-11-171-1/+15
| | | | | | | Add implementation for destroy interface for vcn encode. Signed-off-by: Boyuan Zhang <[email protected]> Acked-by: Christian König <[email protected]>
* radeon/vcn: add encode end frameBoyuan Zhang2017-11-171-1/+2
| | | | | | | Add implementation for end_frame interface for vcn encode. Signed-off-by: Boyuan Zhang <[email protected]> Acked-by: Christian König <[email protected]>
* radeon/vcn: add encode bitstreamBoyuan Zhang2017-11-171-1/+13
| | | | | | | Add implementation for encode_bitstream interface for vcn encode. Signed-off-by: Boyuan Zhang <[email protected]> Acked-by: Christian König <[email protected]>
* radeon/vcn: add encode begin frameBoyuan Zhang2017-11-171-1/+22
| | | | | | | Add implementation for begin_frame interface for vcn encode. Signed-off-by: Boyuan Zhang <[email protected]> Acked-by: Christian König <[email protected]>
* radeon/vcn: add encode header implementationsBoyuan Zhang2017-11-172-0/+241
| | | | | | | | Implement encoding of sps, pps, and silce headers using the newly added h.264 header coding descriptors functions based on h.264 specs. Signed-off-by: Boyuan Zhang <[email protected]> Acked-by: Christian König <[email protected]>
* radeon/vcn: add encode header algorithmsBoyuan Zhang2017-11-172-0/+127
| | | | | | | | | | | | Since bitstream headers, e.g. sps, pps, slice, are encoded in driver side, we need to add corresponding algorithms that required to generate those headers. According to h.264 specs, signed/unsigned interger Exp-Golomb-coded syntax element with left bit first (code_se and code_ue) and unsigned integer using n bits (code_fixed_bits) descriptors function are needed. Therefore, adding those algorithms and related variables and output algorithms here. Signed-off-by: Boyuan Zhang <[email protected]> Acked-by: Christian König <[email protected]>
* radeon/vcn: add ib implementationsBoyuan Zhang2017-11-171-24/+268
| | | | | | | Implement required ibs and command buffer submission interfaces for vcn encode Signed-off-by: Boyuan Zhang <[email protected]> Acked-by: Christian König <[email protected]>
* radeon/vcn: add common encode partBoyuan Zhang2017-11-175-0/+489
| | | | | | | | | Add a skeleton pipe video interface and encode ib interface for video encode on vcn hardware. Add function defines and structures for vcn encode. Update Makefile.sources and meson.build with newly added files. Signed-off-by: Boyuan Zhang <[email protected]> Acked-by: Christian König <[email protected]>
* st/va: implement poc typeBoyuan Zhang2017-11-171-0/+1
| | | | | | | | | pic_order_cnt_type is a required variable when encoding both sps and slice header, therefore we need to get this value from st, e.g. vaapi interface, and then pass it to radeon driver for encoding headers. Signed-off-by: Boyuan Zhang <[email protected]> Acked-by: Christian König <[email protected]>
* vl: add poc typeBoyuan Zhang2017-11-171-0/+1
| | | | | | | | | | | Different from vce encoding, vcn encoding requires driver side to encode bitstream header, such as pps, sps and slice header. pic_order_cnt_type is a required variable when encoding both sps and slice header, therefore we need to add this new variable here, and hold the value passed from st, e.g. vaapi interface Signed-off-by: Boyuan Zhang <[email protected]> Acked-by: Christian König <[email protected]>
* winsys/amdgpu: add vcn enc cs supportBoyuan Zhang2017-11-171-1/+6
| | | | | | | New cs support is needed for vcn encode Signed-off-by: Boyuan Zhang <[email protected]> Acked-by: Christian König <[email protected]>
* radeon/common: add vcn enc ip info queryBoyuan Zhang2017-11-171-1/+9
| | | | | | | New ip info query is needed for vcn encode Signed-off-by: Boyuan Zhang <[email protected]> Acked-by: Christian König <[email protected]>
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