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* radv: ignore pColorBlendState if rasterization is disabledSamuel Pitoiset2019-12-201-5/+21
* radv: tidy up radv_pipeline_init_blend_state()Samuel Pitoiset2019-12-201-112/+115
* radv: ignore pDepthStencilState if rasterization is disabledSamuel Pitoiset2019-12-201-5/+15
* radv: ignore pTessellationState if the pipeline doesn't use tessSamuel Pitoiset2019-12-201-2/+16
* radv: ignore pMultisampleState if rasterization is disabledSamuel Pitoiset2019-12-201-7/+15
* radv: init a default multisample state for the resolve FS pathSamuel Pitoiset2019-12-201-1/+6
* spirv: Implement SPV_KHR_non_semantic_infoCaio Marcelo de Oliveira Filho2019-12-191-0/+29
* turnip: disable B8G8R8 vertex formatsJonathan Marek2019-12-191-6/+6
* util/format: add missing vulkan formatsJonathan Marek2019-12-194-8/+78
* turnip: minor warning fixesJonathan Marek2019-12-192-2/+2
* lima: Rotate dump files after each finished pp frameAndreas Baierl2019-12-195-13/+48
* lima: drop suballocatorVasily Khoruzhick2019-12-194-30/+14
* lima: use single BO for GP outputsVasily Khoruzhick2019-12-193-43/+43
* nir: fix assign_io_var_locations for vertex inputsJonathan Marek2019-12-191-3/+9
* turnip: implement secondary command buffersJonathan Marek2019-12-193-2/+62
* turnip: compute gmem offsets at renderpass creation timeJonathan Marek2019-12-194-66/+82
* turnip: emit_compute_driver_params fixesJonathan Marek2019-12-191-17/+14
* turnip: emit base instance vs driver paramJonathan Marek2019-12-191-0/+53
* freedreno/ir3: support load_base_instanceJonathan Marek2019-12-194-1/+12
* freedreno/registers: document vertex/instance id offset bitsJonathan Marek2019-12-193-3/+8
* st/mesa: release tgsi tokens for shader statesNeha Bhende2019-12-191-0/+4
* Revert "nir/lower_double_ops: relax lower mod()"Juan A. Suarez Romero2019-12-191-15/+6
* freedreno/a6xx: Set up multisample sysmem MRTs correctlyKristian H. Kristensen2019-12-191-3/+1
* freedreno/a6xx: Rewrite compressed blits in a helper functionKristian H. Kristensen2019-12-191-33/+63
* freedreno/a6xx: Move handle_rgba_blit() upKristian H. Kristensen2019-12-191-53/+51
* freedreno/a6xx: Handle srgb blits on the blitterKristian H. Kristensen2019-12-191-10/+20
* freedreno/a6xx: Use A6XX_SP_2D_SRC_FORMAT_MASK macroKristian H. Kristensen2019-12-191-1/+1
* freedreno/a6xx: RB6_R8G8B8 is actually 32 bit RGBXKristian H. Kristensen2019-12-195-12/+12
* freedreno/a6xx: Use blitter for resolve blitsKristian H. Kristensen2019-12-191-24/+5
* freedreno/a6xx: Add fd_resource_swap() helperKristian H. Kristensen2019-12-194-5/+12
* freedreno/a6xx: Pick blitter swap based on resource tilingKristian H. Kristensen2019-12-191-2/+5
* freedreno/a6xx: Program sampler swap based on resource tilingKristian H. Kristensen2019-12-191-16/+4
* freedreno: Add debug flag for forcing linear layoutsKristian H. Kristensen2019-12-193-25/+33
* freedreno/a6xx: Make DEBUG_BLIT_FALLBACK only dump fallbacksKristian H. Kristensen2019-12-191-3/+5
* freedreno/ir3: fix vertex shader sysvals with pre_assign_inputsJonathan Marek2019-12-191-1/+1
* st/va: Convert interlaced NV12 to progressiveThong Thai2019-12-191-4/+48
* pan/midgard: Add uniform/work heuristicAlyssa Rosenzweig2019-12-193-19/+100
* ac: declare an enum for the OOB select field on GFX10Samuel Pitoiset2019-12-1911-25/+35
* radv/gfx10: fix the out-of-bounds check for vertex descriptorsSamuel Pitoiset2019-12-191-1/+5
* nir/lower_double_ops: relax lower mod()Juan A. Suarez Romero2019-12-191-6/+15
* zink: implement nir_texop_txdErik Faye-Lund2019-12-194-11/+26
* zink: enable PIPE_CAP_MIXED_COLORBUFFER_FORMATSErik Faye-Lund2019-12-191-2/+0
* turnip: don't set SP_FS_CTRL_REG0_VARYING if only fragcoord is usedJonathan Marek2019-12-181-1/+1
* turnip: add cache invalidate to fix input attachment casesJonathan Marek2019-12-181-1/+15
* loader: fix close on uninitialized file descriptor valueLionel Landwerlin2019-12-191-1/+4
* freedreno: Fix CP_MEM_TO_REG flag definitionsConnor Abbott2019-12-183-5/+7
* freedreno: Use new macros for CP_WAIT_REG_MEM and CP_WAIT_MEM_GTEConnor Abbott2019-12-183-18/+21
* a6xx: Add more CP packetsConnor Abbott2019-12-187-31/+294
* radv: Limit workgroup size to 1024.Bas Nieuwenhuizen2019-12-181-4/+4
* i965/iris/perf: factor out frequency register captureLionel Landwerlin2019-12-184-61/+56
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