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* radeonsi: don't read the LS output vertex stride from an SGPR in LSMarek Olšák2017-09-071-4/+21
* radeonsi: don't read the number of TCS out vertices from an SGPR in TCSMarek Olšák2017-09-071-2/+15
* radeonsi: don't always apply the PrimID instancing bug workaround on SIMarek Olšák2017-09-071-1/+1
* radeonsi: remove 2 callbacks from si_shader_contextMarek Olšák2017-09-073-17/+13
* winsys/amdgpu: disable local BOs on RavenMarek Olšák2017-09-071-1/+2
* disk_cache: make the thread queue resizable and low priorityMarek Olšák2017-09-071-6/+8
* loader/dri3: Make sure we invalidate a drawable on size changeThomas Hellstrom2017-09-071-0/+2
* loader/dri3: Process event after each fence waitThomas Hellstrom2017-09-071-7/+10
* st/mesa: skip draw calls with pipe_draw_info::count == 0Marek Olšák2017-09-071-1/+6
* radv: do not use a bitfield when dirtying the vertex buffersSamuel Pitoiset2017-09-072-3/+4
* radv: remove unused radv_meta_saved_state::vertex_saved fieldSamuel Pitoiset2017-09-072-8/+0
* mesa: allow user to set MESA_NO_ERROR=0Eric Engestrom2017-09-071-1/+2
* util: rename include guard to avoid clashEric Engestrom2017-09-071-3/+3
* llvmpipe, tgsi: hook up dx10 gather4 opcodeRoland Scheidegger2017-09-072-8/+25
* llvmpipe, draw: increase shader cache limitsRoland Scheidegger2017-09-072-4/+2
* ac/surface: reduce gfx9_surface_layout size.Dave Airlie2017-09-071-2/+3
* radv: reduce radv_amdgpu_winsys struct size.Dave Airlie2017-09-071-3/+3
* radv: reduce radv_image struct size.Dave Airlie2017-09-071-3/+2
* radv: reduce radv_shader_variant struct size.Dave Airlie2017-09-071-1/+1
* radv: reduce radv_cmd_state struct size.Dave Airlie2017-09-071-2/+2
* radv: reduce meta_saved_state struct size.Dave Airlie2017-09-071-4/+3
* nir: put compact into bitfields in nir_variable_dataDave Airlie2017-09-071-1/+1
* anv: Annotate entrypoint table with index and func nameChad Versace2017-09-061-2/+2
* radeon/uvd: fix the assertion check for YUYV formatLeo Liu2017-09-061-3/+5
* intel: Remove unused device info for KBL GT1.5Anuj Phogat2017-09-061-11/+0
* mesa: replace date/time macros with MESA_GIT_SHA1Emil Velikov2017-09-061-3/+7
* mesa: don't use %s for PACKAGE_VERSION macroEmil Velikov2017-09-062-4/+4
* egl/x11: advertise __DRI_USE_INVALIDATE for DRI2Emil Velikov2017-09-061-0/+1
* egl/x11/dri3: adding missing __DRI_BACKGROUND_CALLABLE extensionEmil Velikov2017-09-061-0/+1
* i965: expose RGBA visuals only on AndroidEmil Velikov2017-09-061-1/+22
* swr/rast: FE/Clipper - unify SIMD8/16 functions using simdlib typesTim Rowley2017-09-063-1189/+446
* swr/rast: Remove use of C++14 template variableTim Rowley2017-09-062-6/+14
* swr/rast: SIMD16 FE remove templated immediates workaroundTim Rowley2017-09-061-90/+20
* swr/rast: SIMD16 PA - rename Assemble_simd16 to AssembleTim Rowley2017-09-063-31/+15
* swr/rast: FE/Binner - unify SIMD8/16 functions using simdlib typesTim Rowley2017-09-065-1739/+696
* swr/rast: Removed some trailing whitespace caught during reviewTim Rowley2017-09-063-10/+10
* swr: set caps for VB 4-byte alignmentTim Rowley2017-09-061-3/+6
* swr/rast: Allow gather of floats from fetch shader with 2-4GB offsetsTim Rowley2017-09-062-1/+7
* radv: fix error code when resizing the upload BOSamuel Pitoiset2017-09-061-1/+1
* mesa/st/st_glsl_to_tgsi_temprename.cpp: Fix compilation with MSVCGert Wollny2017-09-061-1/+9
* mesa/st: glsl_to_tgsi: tie in new temporary register merge approachGert Wollny2017-09-061-50/+16
* mesa/st: glsl_to_tgsi: Add test set for evaluation of rename mappingGert Wollny2017-09-061-0/+169
* mesa/st: glsl_to_tgsi: add register rename mapping evaluatorGert Wollny2017-09-063-5/+137
* mesa/st: glsl_to_tgsi: add tests for the new temporary lifetime trackerGert Wollny2017-09-065-4/+1482
* mesa/st: glsl_to_tgsi: implement new temporary register lifetime trackerGert Wollny2017-09-063-0/+943
* mesa/st: glsl_to_tgsi move some helper classes to extra filesGert Wollny2017-09-064-287/+368
* st_glsl_to_tgsi: rewrite rename registers to use array fully.Dave Airlie2017-09-061-29/+26
* radeonsi/gfx9: proper workaround for LS/HS VGPR initialization bugNicolai Hähnle2017-09-065-24/+85
* ac/debug: take ASIC generation into account when printing registersNicolai Hähnle2017-09-062-107/+177
* amd/common: pass chip_class to ac_dump_regNicolai Hähnle2017-09-063-60/+75
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