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* android: enable the radeonsi driverChih-Wei Huang2015-06-094-0/+30
| | | | | | | | | | | | | | | Based on the nice work of Paulo Sergio Travaglia <[email protected]>. The main modifications are: - Include paths for LLVM header files and shared/static libraries - Set C++ flag "c++11" to avoid compiling errors on LLVM header files - Set defines for LLVM - Add GALLIVM source files - Changes path of libelf library for lollipop Signed-off-by: Chih-Wei Huang <[email protected]> Acked-by: Eric Anholt <[email protected]>
* android: generate files by $(call es-gen)Chih-Wei Huang2015-06-091-4/+12
| | | | | | | | | | | | | Use the pre-defined macro es-gen to generate new added files instead of writing new rules manually. The handmade rules that may generate the files before the directory is created result in such an error: /bin/bash: out/target/product/x86/gen/STATIC_LIBRARIES/libmesa_st_mesa_intermediates/main/format_pack.c: No such file or directory make: *** [out/target/product/x86/gen/STATIC_LIBRARIES/libmesa_st_mesa_intermediates/main/format_pack.c] Error 1 Signed-off-by: Chih-Wei Huang <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* android: try to load gallium_dri.so directlyChih-Wei Huang2015-06-091-0/+9
| | | | | | | | | | | This avoids needing hardlinks between all of the DRI driver .so names, since we're the only loader on the system. v2: Add early exit on success (like previous block) and log message on failure. Signed-off-by: Chih-Wei Huang <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* android: Depend on gallium_dri from EGL, instead of linking in gallium.Chih-Wei Huang2015-06-091-80/+3
| | | | | | | | | | | | The Android gallium build used to use gallium_egl, which was removed back in March. Instead, we will now use a normal Mesa libEGL loader with dlopen()ing of a DRI module. v2: add a clean step to rebuild all dri modules properly. v3: Squish the 2 patches doing this together (change by anholt). Signed-off-by: Chih-Wei Huang <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* android: add rules to build a gallium_dri.soChih-Wei Huang2015-06-094-2/+189
| | | | | | | This single .so includes all of the enabled gallium drivers. Signed-off-by: Chih-Wei Huang <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* android: add rules to build gallium/state_trackers/driChih-Wei Huang2015-06-092-2/+67
| | | | | Signed-off-by: Chih-Wei Huang <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* android: export more dirs from libmesa_dri_commonChih-Wei Huang2015-06-091-1/+3
| | | | | | | | The include paths of libmesa_dri_common are also used by modules that need libmesa_dri_common. Signed-off-by: Chih-Wei Huang <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* android: loader: export the path to be includedChih-Wei Huang2015-06-092-1/+2
| | | | | Signed-off-by: Chih-Wei Huang <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965/gen9: Use raw PS invocation count for queriesBen Widawsky2015-06-091-1/+1
| | | | | | | | | | | | Previously the number needed to be divided by 4 to get the proper results. Now the hardware does the right thing. Through experimentation it seems Braswell (CHV) does also need the division by 4. Fixes piglit test: arb_pipeline_statistics_query-frag Signed-off-by: Ben Widawsky <[email protected]> Reviewed-by: Anuj Phogat <[email protected]>
* glsl: fix comment typo: s/accpet/accept/Brian Paul2015-06-091-1/+1
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* mesa: remove some MAX_NV_FRAGMENT_PROGRAM_* macrosBrian Paul2015-06-092-13/+4
| | | | | | | GL_NV_fragment_program support was removed a while ago. This is just some clean-up. Reviewed-by: Matt Turner <[email protected]>
* fs/reg_allocate: Remove the MRF hack helpers from fs_visitorJason Ekstrand2015-06-092-16/+13
| | | | | | | These are helpers that only exist in this one file. No reason to put them in the visitor. Reviewed-by: Neil Roberts <[email protected]>
* i965/fs: Don't let the EOT send message interfere with the MRF hackJason Ekstrand2015-06-092-3/+17
| | | | | | | | | | | | | Previously, we just put the message for the EOT send as high in the file as it would go. This is because the register pre-filling hardware will stop all over the early registers in the file in preparation for the next thread while you're still sending the last message. However, if something happens to spill, then the MRF hack interferes with the EOT send message and, if things aren't scheduled nicely, will stomp on it. Cc: "10.5 10.6" <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90520 Reviewed-by: Neil Roberts <[email protected]>
* rtasm: Generalize executable memory allocator to all Unices.Jose Fonseca2015-06-091-1/+1
| | | | | | | | | | We're only using fairly portable standard Unix calls here, so might as well save ourselves future trouble by enabling on all Unices by default. https://bugs.freedesktop.org/show_bug.cgi?id=90904 Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Roland Scheidegger <[email protected]>
* i965/fs: Drop fs_inst::force_uncompressed.Francisco Jerez2015-06-091-1/+0
| | | | | | This is now unused. Saves a whole bit of memory per instruction. Reviewed-by: Matt Turner <[email protected]>
* i965/fs: Remove dead IR construction code from the visitor.Francisco Jerez2015-06-094-439/+0
| | | | Reviewed-by: Matt Turner <[email protected]>
* i965/fs: Migrate test_fs_cmod_propagation to the IR builder.Francisco Jerez2015-06-091-52/+50
| | | | | | | v2: Use set_predicate/condmod. Use fs_builder::OPCODE instead of ::emit. Reviewed-by: Matt Turner <[email protected]>
* i965/fs: Migrate test_fs_saturate_propagation to the IR builder.Francisco Jerez2015-06-091-35/+34
| | | | | | v2: Use set_saturate. Use fs_builder::OPCODE instead of ::emit. Reviewed-by: Matt Turner <[email protected]>
* i965/fs: Migrate translation of NIR texturing instructions to the IR builder.Francisco Jerez2015-06-092-5/+6
| | | | | | v2: Don't remove assignments of base_ir just yet. Reviewed-by: Matt Turner <[email protected]>
* i965/fs: Migrate translation of NIR intrinsics to the IR builder.Francisco Jerez2015-06-092-41/+42
| | | | | | v2: Use fs_builder::SEL instead of ::emit. Use set_condmod(). Reviewed-by: Matt Turner <[email protected]>
* i965/fs: Migrate translation of NIR ALU instructions to the IR builder.Francisco Jerez2015-06-093-99/+99
| | | | Reviewed-by: Matt Turner <[email protected]>
* i965/fs: Migrate translation of NIR control flow to the IR builder.Francisco Jerez2015-06-092-12/+14
| | | | Reviewed-by: Matt Turner <[email protected]>
* i965/fs: Migrate NIR variable handling to the IR builder.Francisco Jerez2015-06-091-11/+10
| | | | Reviewed-by: Matt Turner <[email protected]>
* i965/fs: Migrate NIR emit_percomp() to the IR builder.Francisco Jerez2015-06-092-7/+12
| | | | Reviewed-by: Matt Turner <[email protected]>
* i965/fs: Migrate CS terminate message to the IR builder.Francisco Jerez2015-06-091-3/+2
| | | | Reviewed-by: Matt Turner <[email protected]>
* i965/fs: Migrate VS output writes to the IR builder.Francisco Jerez2015-06-091-13/+11
| | | | Reviewed-by: Matt Turner <[email protected]>
* i965/fs: Migrate FS framebuffer writes to the IR builder.Francisco Jerez2015-06-093-34/+35
| | | | | | | | | | | | | | The explicit call to fs_builder::group() in emit_single_fb_write() is required by the builder (otherwise the assertion in fs_builder::emit() would fail) because the subsequent LOAD_PAYLOAD and FB_WRITE instructions are in some cases emitted with a non-native execution width. The previous code would always use the channel enables for the first quarter, which is dubious but probably worked in practice because FB writes are never emitted inside non-uniform control flow and we don't pass the kill-pixel mask via predication in the cases where we have to fall-back to SIMD8 writes. Reviewed-by: Matt Turner <[email protected]>
* i965/fs: Migrate FS alpha test to the IR builder.Francisco Jerez2015-06-091-5/+5
| | | | Reviewed-by: Matt Turner <[email protected]>
* i965/fs: Migrate FS discard handling to the IR builder.Francisco Jerez2015-06-091-3/+3
| | | | Reviewed-by: Matt Turner <[email protected]>
* i965/fs: Migrate FS gl_SamplePosition/ID computation code to the IR builder.Francisco Jerez2015-06-091-25/+24
| | | | | | v2: Use fs_builder::AND/SHR/MOV instead of ::emit. Reviewed-by: Matt Turner <[email protected]>
* i965/fs: Migrate FS interpolation code to the IR builder.Francisco Jerez2015-06-092-48/+46
| | | | | | v2: Fix some preexisting trivial codestyle issues. Reviewed-by: Matt Turner <[email protected]>
* i965/fs: Migrate shader time to the IR builder.Francisco Jerez2015-06-092-36/+23
| | | | | | v2: Change null register destination type to UD so it can be compacted. Reviewed-by: Matt Turner <[email protected]>
* i965/fs: Migrate untyped surface read and atomic to the IR builder.Francisco Jerez2015-06-091-28/+27
| | | | Reviewed-by: Matt Turner <[email protected]>
* i965/fs: Migrate texturing implementation to the IR builder.Francisco Jerez2015-06-091-81/+78
| | | | | | v2: Remove tabs from modified lines. Reviewed-by: Matt Turner <[email protected]>
* i965/fs: Migrate pull constant loads to the IR builder.Francisco Jerez2015-06-093-31/+21
| | | | Reviewed-by: Matt Turner <[email protected]>
* i965/fs: Migrate Gen4 send dependency workarounds to the IR builder.Francisco Jerez2015-06-092-17/+11
| | | | | | v2: Change brw_null_reg() to bld.null_reg_f(). Reviewed-by: Matt Turner <[email protected]>
* i965/fs: Migrate lower_integer_multiplication to the IR builder.Francisco Jerez2015-06-091-13/+11
| | | | Reviewed-by: Matt Turner <[email protected]>
* i965/fs: Migrate lower_load_payload to the IR builder.Francisco Jerez2015-06-091-23/+11
| | | | Reviewed-by: Matt Turner <[email protected]>
* i965/fs: Migrate register spills and fills to the IR builder.Francisco Jerez2015-06-091-14/+15
| | | | | | | | | | | | | | | Yes, it's incorrect to use the 0-th channel enable group unconditionally without considering the execution and regioning controls of the instruction that uses the spilled value, but it matches the previous behaviour exactly, the builder just makes the preexisting problem more obvious because emitting an instruction of non-native SIMD width without having called .group() or .exec_all() explicitly would have led to an assertion failure. I'll fix the problem in a follow-up series, as the solution is going to be non-trivial. Reviewed-by: Matt Turner <[email protected]>
* i965/fs: Migrate try_replace_with_sel to the IR builder.Francisco Jerez2015-06-091-9/+9
| | | | Reviewed-by: Matt Turner <[email protected]>
* i965/fs: Migrate opt_sampler_eot to the IR builder.Francisco Jerez2015-06-091-2/+3
| | | | Reviewed-by: Matt Turner <[email protected]>
* i965/fs: Migrate opt_peephole_sel to the IR builder.Francisco Jerez2015-06-091-13/+12
| | | | Reviewed-by: Matt Turner <[email protected]>
* i965/fs: Create and emit instructions in one step in opt_peephole_sel.Francisco Jerez2015-06-091-24/+20
| | | | | | | | | | This simplifies opt_peephole_sel() slightly by emitting the SEL instructions immediately after they are created, what makes the sel_inst and mov_imm_inst arrays unnecessary and will make it possible to get rid of the explicit inserts when the pass is migrated to the IR builder. Reviewed-by: Matt Turner <[email protected]>
* i965/fs: Migrate opt_cse to the IR builder.Francisco Jerez2015-06-091-15/+12
| | | | Reviewed-by: Matt Turner <[email protected]>
* i965/fs: Don't drop force_writemask_all and _sechalf when copying a CSE ↵Francisco Jerez2015-06-091-1/+2
| | | | | | | | | | temporary. LOAD_PAYLOAD instructions need the same treatment as any other generator instructions, at least FB writes and typed surface messages will need a payload built with non-zero execution controls. Reviewed-by: Matt Turner <[email protected]>
* i965/vec4: Take into account all instruction fields in CSE instructions_match().Francisco Jerez2015-06-091-0/+8
| | | | | | | | | | Most of these fields affect the behaviour of the instruction, but apparently we currently don't CSE the kind of instructions for which these fields could make a difference in the VEC4 back-end. That's likely to change soon though when we start using send-from-GRF for texture sampling and surface access messages. Reviewed-by: Matt Turner <[email protected]>
* i965/fs: Take into account all instruction fields in CSE instructions_match().Francisco Jerez2015-06-091-8/+12
| | | | | | | | Most of these fields affect the behaviour of the instruction so it could actually break the program if we CSE a pair of otherwise matching instructions with different values of these fields. Reviewed-by: Matt Turner <[email protected]>
* i965/fs: Migrate opt_peephole_predicated_break to the IR builder.Francisco Jerez2015-06-091-3/+3
| | | | Reviewed-by: Matt Turner <[email protected]>
* i965/fs: Migrate opt_combine_constants to the IR builder.Francisco Jerez2015-06-091-9/+10
| | | | Reviewed-by: Matt Turner <[email protected]>
* i965/fs: Allocate a common IR builder object in fs_visitor.Francisco Jerez2015-06-093-1/+16
| | | | | | | v2: Call fs_builder::at_end() to point the builder at the end of the program explicitly. Reviewed-by: Matt Turner <[email protected]>
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-23 22:44:05 +0000