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* ilo: support mapping with a staging system bufferChia-I Wu2013-05-091-0/+77
| | | | | It can be used for unpacking compressed texture on-the-fly or to support explicit transfer flushing.
* ilo: allow for different mapping methodsChia-I Wu2013-05-091-115/+187
| | | | | We want to or need to use a different mapping method when when the resource is busy, the bo format differs from the requested format, and etc.
* ilo: allow bo format to differ from that requestedChia-I Wu2013-05-092-14/+22
| | | | | For separate stencil buffer or formats not supported natively, the real format of the bo may differ from that requested.
* draw/llvm: Add additional llvm optimization passesStéphane Marchesin2013-05-081-0/+3
| | | | | | | | | | | | It helps a bit with vertex shader performance on i915g (a couple percent faster with openarena). I have tried most other passes, and they weren't showing any measurable improvement. Note that my vertex shaders didn't have loops, so maybe the loop optimizations could still be useful in the future. Reviewed-by: Brian Paul <[email protected]>
* i965: Sync brw_format_for_mesa_format() table with new Mesa formats.Eric Anholt2013-05-081-1/+31
| | | | | | I'm not filling them all in, to prevent any breakage in this commit. Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Update the surface formats table from the current specs.Eric Anholt2013-05-081-0/+65
| | | | | | | | | | | Unfortunately the surface formats table is now splattered across multiple chapters. All surface format enums from brw_defines.h are present, but only support for them that is mentioned in the public specs is included here. v2 (from Ken): Mark R32G32B32A32_SFIXED as unsupported on Ivybridge. Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Add surface format defines from the public specs.Eric Anholt2013-05-081-0/+45
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* mesa/program: Don't copy propagate from swizzles.Fabian Bieler2013-05-081-0/+2
| | | | | | | | | | | | | | | | | | | | | Do not propagate a copy if source and destination are identical. Otherwise code like MOV TEMP[0].xyzw, TEMP[0].wzyx MOV TEMP[1].xyzw, TEMP[0].xyzw is changed to MOV TEMP[0].xyzw, TEMP[0].wzyx MOV TEMP[1].xyzw, TEMP[0].wzyx This fixes Piglit test shaders/glsl-copy-propagation-self-2 for drivers that use Mesa IR. NOTE: This is a candidate for the stable branches. Signed-off-by: Fabian Bieler <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* mesa/st: Don't copy propagate from swizzles.Fabian Bieler2013-05-081-0/+2
| | | | | | | | | | | | | | | | | | | | Do not propagate a copy if source and destination are identical. Otherwise code like MOV TEMP[0].xyzw, TEMP[0].wzyx MOV TEMP[1].xyzw, TEMP[0].xyzw is changed to MOV TEMP[0].xyzw, TEMP[0].wzyx MOV TEMP[1].xyzw, TEMP[0].wzyx This fixes Piglit test shaders/glsl-copy-propagation-self-2 for gallium drivers. NOTE: This is a candidate for the stable branches. Signed-off-by: Fabian Bieler <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* i965: Fix hangs on HSW since the gen6 blorp fix.Eric Anholt2013-05-081-2/+101
| | | | | | | | | | | The constant packets for gen6 are too small for gen7, and while IVB seems happy with them HSW blows up. Fix it by emitting the correct packets on gen7, for all stages. v2: Include the packets instead of just skipping them. NOTE: This is a candidate for the stable branches. Reviewed-and-tested-by: Chad Versace <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* egl/android: Fix error condition for EGL_ANDROID_image_native_bufferChad Versace2013-05-081-2/+14
| | | | | | | | | | | | | Emit EGL_BAD_CONTEXT if the user passes a context to eglCreateImageKHR(type=EGL_ANDROID_image_native_buffer). From the EGL_ANDROID_image_native_buffer spec: * If <target> is EGL_NATIVE_BUFFER_ANDROID and <ctx> is not EGL_NO_CONTEXT, the error EGL_BAD_CONTEXT is generated. Note: This is a candidate for the stable branches. Reviewed-by: Tapani Pälli <[email protected]> Signed-off-by: Chad Versace <[email protected]>
* i915: Use Y tiling for texturesStéphane Marchesin2013-05-081-2/+7
| | | | | | | | | | | This basically reverts commit 2acc7193743199701f8f6d1877a59ece0ec4fa5b. With the previous change, we're not batchbuffer limited any longer. So we actually start seeing a performance difference between X and Y tiling. X tiling is funny because it is faster for screen-aligned quads but slower in games. So let's use Y tiling which is 10% faster overall.
* i915g: Optimize batchbuffer sizesStéphane Marchesin2013-05-082-4/+6
| | | | | | | Now that we don't throttle at every batchbuffer, we can shrink the size of batchbuffers to achieve early flushing. This gives a significant speed boost in a lot of games (on the order of 20%).
* i915g: Add more PIPE_CAP_* supportStéphane Marchesin2013-05-081-0/+9
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* ilo: remove our own type inferenceChia-I Wu2013-05-081-97/+27
| | | | tgsi_opcode_infer_{src,dst}_type() works just fine.
* ilo: use tgsi_util_get_texture_coord_dim()Chia-I Wu2013-05-083-92/+4
| | | | And remove toy_tgsi_get_texture_coord_dim().
* tgsi: fix operand type of TGSI_OPCODE_NOTChia-I Wu2013-05-082-1/+2
| | | | | | | | | It should be TGSI_TYPE_UNSIGNED, not TGSI_TYPE_FLOAT. Fixed also gallivm not_emit_cpu() to use uint build context. Signed-off-by: Chia-I Wu <[email protected]> Acked-by: Roland Scheidegger <[email protected]>
* tgsi: refactor tgsi_opcode_infer_src_type()Chia-I Wu2013-05-081-35/+9
| | | | | | | Call tgsi_opcode_infer_type() from tgsi_opcode_infer_src_type(). Signed-off-by: Chia-I Wu <[email protected]> Acked-by: Roland Scheidegger <[email protected]>
* tgsi: refactor tgsi_opcode_infer_dst_type()Chia-I Wu2013-05-081-25/+35
| | | | | | | | | | | | | Move the body of tgsi_opcode_infer_dst_type() to a new helper function, tgsi_opcode_infer_type(), and call the helper function from tgsi_opcode_infer_dst_type(). The diff looks complicated simply because the code is moved around. A following commit will make tgsi_opcode_infer_src_type() call tgsi_opcode_infer_type(). Signed-off-by: Chia-I Wu <[email protected]> Acked-by: Roland Scheidegger <[email protected]>
* tgsi: reorder opcodes in opcode type inferenceChia-I Wu2013-05-081-24/+24
| | | | | | | | | Reorder opcodes by their assigned numbers. This makes it easier to see the differences between tgsi_opcode_infer_src_type() and tgsi_opcode_infer_dst_type(). Signed-off-by: Chia-I Wu <[email protected]> Acked-by: Roland Scheidegger <[email protected]>
* tgsi: clean up exec_tex()Chia-I Wu2013-05-081-168/+52
| | | | | | | | | | | | Make use of tgsi_util_get_texture_coord_dim() to replace the big switch table. There is a subtle difference with this change. When TXP is used with an array texture, the layer is now also projected. This behavior matches the TGSI doc. Since GLSL does not allow TXP on an array texture, I am not sure which behavior is correct or preferred. Signed-off-by: Chia-I Wu <[email protected]> Acked-by: Roland Scheidegger <[email protected]>
* tgsi: add tgsi_util_get_texture_coord_dim()Chia-I Wu2013-05-082-0/+94
| | | | | | | | | | | | This util function returns the dimension of the texture coordinates for a texture target, and the location of the shadow reference value. For example, when the texture target is TGSI_TEXTURE_SHADOW2D, the dimension of the texture coordinates is 2, and the location of the ref value is 2 (that is, the Z channel). Signed-off-by: Chia-I Wu <[email protected]> Acked-by: Roland Scheidegger <[email protected]>
* nv50: initialize kick_notify callback in nv50_createBryan Cain2013-05-071-0/+1
| | | | | | Fixes infinite loop on startup in Portal and Left 4 Dead 2. NOTE: This is a candidate for the 9.0 and 9.1 branches.
* i965: Use Y-tiled blits to untile for cached mappings of miptrees.Eric Anholt2013-05-071-1/+2
| | | | | | | | Fixes a regression in firefox's unaccelerated compositing path for WebGL with the introduction of Y tiling. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=64213 Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Add support for Y-tiled blits on gen6+.Eric Anholt2013-05-072-3/+42
| | | | | Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* i965: Count occlusion query samples for CopyPixels using the 2D engine.Eric Anholt2013-05-071-0/+3
| | | | | | | | | | We accidentally "fixed" the piglit test for this when introducing Y tiling, since this path stopped being executed. In reenabling this path for Y tiling, we ended up regressing it again, so just fix it. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=59439 Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* egl/wayland: Implement EGL_EXT_swap_buffers_with_damageRobert Bragg2013-05-071-3/+26
| | | | | Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]>
* egl: Add extension infrastructure for EGL_EXT_swap_buffers_with_damageRobert Bragg2013-05-074-0/+41
| | | | | Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]>
* gallium: more tgsi documentation updatesRoland Scheidegger2013-05-071-131/+250
| | | | | | | | | Adds the remaining integer opcodes, and some opcodes are moved to more appropriate places, along with getting rid of the (already nearly empty) ps_2_x section. Though the CAP bits for some of these are still a bit in the air so the documentation isn't quite as watertight as is desirable. Reviewed-by: Jose Fonseca <[email protected]>
* ilo: Add missing break statement in aos_tex TGSI_OPCODE_TEX2 case.Vinson Lee2013-05-071-0/+1
| | | | | | | Fixes "Missing break in switch" defect reported by Coverity. Signed-off-by: Vinson Lee <[email protected]> Reviewed-by: Chia-I Wu <[email protected]>
* r600g/sb: optimize some cases for CNDxx instructionsVadim Girlin2013-05-072-5/+81
| | | | | | | | | | | | | | We can replace CNDxx with MOV (and possibly eliminate after propagation) in following cases: If src1 is equal to src2 in CNDxx instruction then the result doesn't depend on condition and we can replace the instruction with "MOV dst, src1". If src0 is const then we can evaluate the condition at compile time and also replace it with MOV. Signed-off-by: Vadim Girlin <[email protected]>
* r600g/sb: fix memory leaksVadim Girlin2013-05-072-1/+7
| | | | Signed-off-by: Vadim Girlin <[email protected]>
* r600g/sb: fix kcache handling on r6xxVadim Girlin2013-05-071-1/+5
| | | | | | | | | Use the same limit for kcache constants in alu group on r6xx as on other chips (two const pairs). Relaxing this will require additional checks to make sure that all 4 consts in the group come from 2 kcache sets (clause limit), probably without noticeable improvements of shader performance. Signed-off-by: Vadim Girlin <[email protected]>
* intel: Remove renderbuffer delete setup from texture wrapping.Eric Anholt2013-05-061-1/+0
| | | | | | This is already set by intel_new_renderbuffer(). Reviewed-by: Kenneth Graunke <[email protected]>
* mesa: Make Mesa core set up wrapped texture renderbuffer state.Eric Anholt2013-05-065-34/+7
| | | | | | | | | | Everyone was doing effectively the same thing, except for some funky code reuse in Intel, and swrast mistakenly recomputing _BaseFormat instead of using the texture's _BaseFormat. swrast's sRGB handling is left in place, though it should be done by using _mesa_get_render_format() at render time instead (as-is, it will miss updates to GL_FRAMEBUFFER_SRGB). Reviewed-by: Kenneth Graunke <[email protected]>
* intel: Simplify renderbuffer-for-texture width setup.Eric Anholt2013-05-061-11/+2
| | | | | | | | We're looking for the logical width of our level, which is what image->Width2/Height2 is. The previous code relied on MSAA textures being only level 0. Reviewed-by: Kenneth Graunke <[email protected]>
* mesa: Make core Mesa allocate the texture renderbuffer wrapper.Eric Anholt2013-05-068-101/+56
| | | | | | Every driver did the same thing. Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Use brw_blorp_blit_miptrees() for CopyTexSubImage().Eric Anholt2013-05-063-77/+41
| | | | | | | Now that depth resolves are handled there, we don't need to make the temporary renderbuffer. Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Move blorp resolve setup into brw_blorp_blit_miptrees().Eric Anholt2013-05-062-18/+5
| | | | | | | | | There was some comment about trying to avoid marking resolves in updownsample, but if the downsample is never actually rendered to, then the required resolve tracked in the downsample will never be executed, so who cares? Reviewed-by: Kenneth Graunke <[email protected]>
* gallivm: Fix build for LLVM < 3.3Tom Stellard2013-05-061-0/+6
| | | | | The C API versions of the LLVM multithreaded functions were added in LLVM 3.3.
* r600g/llvm: Parse config values in register / value pairsTom Stellard2013-05-062-4/+31
| | | | Rather than relying on a predetermined order for the config values.
* r600g/llvm: Don't feed LLVM output through r600_bytecode_build()Tom Stellard2013-05-064-395/+21
| | | | | The LLVM backend emits raw ISA now, so we can just its output unmodified.
* r600g/llvm: Don't emit CALL_FS for vertex shadersTom Stellard2013-05-062-8/+10
| | | | The LLVM backend takes care of this now.
* i965: Lower bitfieldInsert.Matt Turner2013-05-061-0/+4
| | | | | | | | | | | | v2: Only lower bitfieldInsert to BFM+BFI (and don't lower bitfieldExtract at all) since three-source instructions are now usable in the vertex shader. v3: Lower bitfield_insert in the same pass with everything else, since it doesn't produce any instructions to be lowered (the other two lowering passes that were in a previous iteration of this series emitted subtractions which needed to be lowered). Reviewed-by: Chris Forbes <[email protected]> [v2]
* i965/vs: Add support for bit instructions.Matt Turner2013-05-064-1/+106
| | | | | | | | | | | v2: Rebase on LRP addition. Use fix_3src_operand() when emitting BFE and BFI2. Add BFE and BFI2 to is_3src_inst check in brw_vec4_copy_propagation.cpp. Subtract result of FBH from 31 (unless an error) to convert MSB counts to LSB counts Reviewed-by: Chris Forbes <[email protected]>
* i965/fs: Add support for bit instructions.Matt Turner2013-05-065-0/+142
| | | | | | | | | | | | Don't bother scalarizing ir_binop_bfm, since its results are identical for all channels. v2: Subtract result of FBH from 31 (unless an error) to convert MSB counts to LSB counts. v3: Use op0->clone() in ir_triop_bfi to prevent (var_ref channel_expressions) from appearing multiple times in the IR. Reviewed-by: Chris Forbes <[email protected]> [v2]
* i965: Add support for emitting and disassembling bit instructions.Matt Turner2013-05-064-0/+28
| | | | | | | | | | | | Specifically bfe - for bitfieldExtract() bfi1 and bfi2 - for bitfieldInsert() bfrev - for bitfieldReverse() cbit - for bitCount() fbh - for findMSB() fbl - for findLSB() Reviewed-by: Chris Forbes <[email protected]>
* i965: Print the correct dst and shared-src types for 3-src instructions.Matt Turner2013-05-061-4/+22
| | | | Reviewed-by: Chris Forbes <[email protected]>
* i965/gen7: Set src/dst types for 3-src instructions.Matt Turner2013-05-061-4/+36
| | | | | | | | | | | | Also update asserts to allow BFE and BFI2, which take (unsigned) doubleword arguments. v2: Allow BRW_REGISTER_TYPE_UD for src1 and src2 as well. Assert that src2.type (instead of src0.type) matches dest.type since it's the primary argument and src0 and src1 might correctly have different types. Reviewed-by: Chris Forbes <[email protected]> [v1]
* i965: Add 3-src destination and shared-source type macros.Matt Turner2013-05-061-0/+11
| | | | Reviewed-by: Chris Forbes <[email protected]>
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