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* Revert "mesa: add missing RGB9_E5 format in _mesa_base_fbo_format"Antia Puentes2018-01-311-3/+0
* winsys/radeon: Compute is_displayable in surf_drm_to_winsysMichel Dänzer2018-01-311-0/+3
* radv: remove predication on cache flushesMatthew Nicholls2018-01-314-18/+13
* mesa: fix broken glGet*(GL_POLYGON_MODE) queryBrian Paul2018-01-302-3/+3
* virgl: also remove dimension on indirect.Dave Airlie2018-01-311-1/+0
* radeonsi: remove DBG_PRECOMPILEMarek Olšák2018-01-313-51/+0
* radeonsi: print shader-db stats for main parts, not final binariesMarek Olšák2018-01-313-13/+23
* radeonsi: move max_simd_waves computation into a separate functionMarek Olšák2018-01-312-12/+23
* mesa: fix glGet MAX_VERTEX_ATTRIB queriesMarek Olšák2018-01-311-3/+3
* anv/cmd_buffer: Re-emit the pipeline at every subpassJason Ekstrand2018-01-301-0/+11
* nir: Distribute binary operations with constants into bcselIan Romanick2018-01-301-0/+15
* nir: Rearrange logic op-compounded integer comparesIan Romanick2018-01-301-0/+35
* nir: Rearrange and-compounded float comparesIan Romanick2018-01-301-0/+8
* nir: Separate a weird compare with zero to two compares with zeroIan Romanick2018-01-301-0/+2
* nir: Simplify min and max of b2fIan Romanick2018-01-301-0/+5
* nir: Undo possible damage caused by rearranging or-compounded float comparesIan Romanick2018-01-301-0/+9
* nir: Be more conservative about rearranging or-compounded comparesIan Romanick2018-01-301-4/+9
* nir: See through an fneg to apply existing optimizationsIan Romanick2018-01-301-3/+6
* st/glsl_to_nir: disable io lowering and array splitting of fs inputsTimothy Arceri2018-01-311-4/+18
* nir: add lower_all_io_to_temps flagTimothy Arceri2018-01-314-0/+5
* nir/st_glsl_to_nir: add param to disable splitting of inputsTimothy Arceri2018-01-313-11/+16
* st/glsl_to_nir: copy nir compiler options to contextTimothy Arceri2018-01-312-8/+22
* radeonsi/nir: add input support for arrays that have not been copied to temps...Timothy Arceri2018-01-311-67/+79
* ac/radeonsi: add lookup_interp_param and load_sample_position to the abiTimothy Arceri2018-01-313-29/+44
* radeonsi/nir: add prim_mask to the abiTimothy Arceri2018-01-313-9/+10
* radeonsi/nir: adjust load_sample_position() to be shared between backendsTimothy Arceri2018-01-311-2/+3
* radeonsi/nir: add si_nir_lookup_interp_param() helperTimothy Arceri2018-01-313-0/+42
* ac/nir_to_llvm: move some interp defines to the headerTimothy Arceri2018-01-312-4/+5
* radeonsi/nir: move the interpolation qualifier scanningTimothy Arceri2018-01-311-16/+36
* radeonsi/nir: add interpolate at intrinsics to scan_instruction()Timothy Arceri2018-01-311-0/+30
* radv: Merge raster state with PM4 generation.Bas Nieuwenhuizen2018-01-302-75/+50
* radv: Move gs state out of pipeline.Bas Nieuwenhuizen2018-01-302-43/+43
* radv: Split out cliprect rule generation.Bas Nieuwenhuizen2018-01-302-25/+33
* radv: Merge VGT_GS_MODE computation with PM4 generation.Bas Nieuwenhuizen2018-01-302-28/+25
* radv: Split out processing the vertex input state.Bas Nieuwenhuizen2018-01-301-35/+43
* radv: Move tessellation state out of pipeline.Bas Nieuwenhuizen2018-01-302-50/+58
* radv: Move blend state out of pipeline.Bas Nieuwenhuizen2018-01-302-67/+72
* radv: Split out generating VGT_SHADER_STAGES_EN.Bas Nieuwenhuizen2018-01-302-24/+27
* radv: Split out the ia_multi_vgt_param precomputation.Bas Nieuwenhuizen2018-01-303-91/+106
* radv: Split out db_shader_control computation.Bas Nieuwenhuizen2018-01-302-22/+22
* radv: Compute shader_z_format when emitting it.Bas Nieuwenhuizen2018-01-302-8/+3
* radv: Merge depth stencil state with PM4 generation.Bas Nieuwenhuizen2018-01-302-73/+58
* radv: Merge ps_input_cntl computation with PM4 generation.Bas Nieuwenhuizen2018-01-302-83/+79
* radv: Merge vtx_reuse_depth computation with PM4 generation.Bas Nieuwenhuizen2018-01-302-8/+6
* radv: Merge vs state computation with PM4 generation.Bas Nieuwenhuizen2018-01-302-58/+34
* radv: Merge binning state generation with pm4 emission.Bas Nieuwenhuizen2018-01-302-35/+19
* radv: Constify some pipeline helpers.Bas Nieuwenhuizen2018-01-302-6/+6
* radv: Add PM4 pregeneration for compute pipelines.Bas Nieuwenhuizen2018-01-302-58/+68
* radv: Record a PM4 sequence for graphics pipeline switches.Bas Nieuwenhuizen2018-01-303-451/+483
* radv: Determine unneeded dynamic states.Bas Nieuwenhuizen2018-01-303-38/+64
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