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* radv/gfx10: invalidate everything in L2 when shaders read dataSamuel Pitoiset2019-07-121-1/+3
* radv/gfx10: fix wrong emission of GE_CNTLSamuel Pitoiset2019-07-121-1/+1
* radv: add more assertions to make sure packets are correctly emittedSamuel Pitoiset2019-07-121-3/+3
* v3d: use inc/dec tmu operation with image atomic sub/add of 1Alejandro Piñeiro2019-07-121-5/+11
* v3d: refactor some code from v3d40_vir_emit_image_load_storeAlejandro Piñeiro2019-07-121-33/+29
* v3d: use inc/dec tmu operation with atomic sub/add of 1Alejandro Piñeiro2019-07-122-6/+30
* v3d: remove redefinition of tmu operations on nir_to_virAlejandro Piñeiro2019-07-121-38/+21
* v3d: tweak initial comment on pack generator scriptAlejandro Piñeiro2019-07-121-1/+1
* glsl/link_varyings: Fix hash table leakYevhenii Kolesnikov2019-07-121-9/+8
* iris: Simplify devinfo access in calculate_result_on_gpu()Kenneth Graunke2019-07-121-3/+2
* v3d: remove unused definitionsIago Toral Quiroga2019-07-121-7/+0
* v3d: move implementation of some intrinsics to separate helpersIago Toral Quiroga2019-07-121-78/+90
* v3d: emit correct lowering for logic ops with RGB10A2 render targetsIago Toral Quiroga2019-07-121-12/+64
* v3d: emit correct lowering for logic ops with integer render targetsIago Toral Quiroga2019-07-122-9/+47
* v3d: add lowering for OpenGL logic operationsIago Toral Quiroga2019-07-124-0/+279
* v3d: acquire scoreboard lock before first tlb readIago Toral Quiroga2019-07-124-0/+36
* v3d: implement tile buffer color read intrinsicIago Toral Quiroga2019-07-121-0/+100
* nir: add a new v3d-specific intrinsic for tile buffer color readsIago Toral Quiroga2019-07-121-0/+9
* v3d: fix size of color_reads and sample_colors arraysIago Toral Quiroga2019-07-121-2/+2
* v3d: add color formats and swizzles to the fragment shader keyIago Toral Quiroga2019-07-122-0/+20
* v3d: add helpers to emit ldtlb and ldtlbu signalsIago Toral Quiroga2019-07-121-0/+24
* v3d: handle tlb read dependency tracking as if they were writesIago Toral Quiroga2019-07-121-1/+1
* v3d: instructions with the ldtlb and ldtlbu signals are tlb instructionsIago Toral Quiroga2019-07-121-0/+3
* v3d: tlb loads cannot be removedIago Toral Quiroga2019-07-121-0/+2
* v3d: the ldtlbu signal reads an implicit uniformIago Toral Quiroga2019-07-121-0/+1
* v3d: handle ldtlb and ldtlbu signals during disassemblyIago Toral Quiroga2019-07-121-0/+2
* radv: report shader stage name when dumping LLVM IRSamuel Pitoiset2019-07-121-4/+17
* radv: tidy up radv_get_shader_name() and add NGG stagesSamuel Pitoiset2019-07-123-12/+32
* radv/gfx10: update OVERWRITE_COMBINER_{MRT_SHARING,WATERMARK}Samuel Pitoiset2019-07-121-16/+4
* radv/gfx10: do not set alignment on the ngg_emit pointerSamuel Pitoiset2019-07-121-1/+0
* radv/gfx10: fix exporting clip/cull distances for GSSamuel Pitoiset2019-07-121-1/+2
* radv/gfx10: fix exporting the subpass view index for GSSamuel Pitoiset2019-07-121-1/+15
* mesa: save/restore SSO flag when using ARB_get_program_binaryTimothy Arceri2019-07-121-0/+4
* pan/midgard: Correct component count clamping PSIZAlyssa Rosenzweig2019-07-111-1/+2
* panfrost: Remove unused display target fieldAlyssa Rosenzweig2019-07-112-4/+0
* panfrost/ci: Update expectationsAlyssa Rosenzweig2019-07-111-2/+1
* radv: only enable the GS copy shader stage if GS is enabledSamuel Pitoiset2019-07-111-1/+1
* freedreno: Add dependency on the xml build to the winsys.Eric Anholt2019-07-111-1/+4
* iris: Disable SIMD32 when using a 16x MSAA framebuffer.Kenneth Graunke2019-07-111-7/+24
* nir/algebraic: Recognize open-coded flrp(a, b, a)Ian Romanick2019-07-111-0/+24
* nir/algebraic: Rearrange 1-((1-a) * (1-b)) into flrp-friendly formIan Romanick2019-07-111-0/+10
* nir/algebraic: Reassociate fadd into fmul in DPH-like patternIan Romanick2019-07-112-0/+36
* nir/algebraic: Recognize open-coded flrp(-1, 1, a) and flrp(1, -1, a)Ian Romanick2019-07-111-0/+12
* nir: intel/vec4: Add flag to disable some algebraic optimizationsIan Romanick2019-07-112-0/+11
* intel/vec4: Try to emit immediate sources for MOVIan Romanick2019-07-111-4/+14
* intel/vec4: Try to emit a VF source in try_immediate_sourceIan Romanick2019-07-111-12/+33
* intel/vec4: Try to emit a single load for multiple 3-src instruction operandsIan Romanick2019-07-112-4/+36
* intel/vec4: Refactor operand fixing for ffma and flrpIan Romanick2019-07-112-8/+16
* panfrost: Wire up GLES2-class polygon offsetAlyssa Rosenzweig2019-07-111-0/+11
* pan/decode: Depth units/factor are identical to GLAlyssa Rosenzweig2019-07-112-10/+2
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