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* anv: Implement VK_EXT_texel_buffer_alignmentJason Ekstrand2019-07-022-0/+38
* vulkan: Update the XML and headers to 1.1.113Jason Ekstrand2019-07-021-8/+63
* spirv: Ignore ArrayStride in OpPtrAccessChain for WorkgroupCaio Marcelo de Oliveira Filho2019-07-021-4/+6
* nouveau: handle new CAPSKarol Herbst2019-07-022-0/+26
* intel/fs: Use nir_lower_interpolation on gen11+Jason Ekstrand2019-07-024-48/+3
* intel/fs: Implement nir_intrinsic_load_fs_input_interp_deltasJason Ekstrand2019-07-022-1/+14
* intel/fs: Actually implement the load_barycentric intrinsicsJason Ekstrand2019-07-022-12/+93
* nir: add pass to lower load_interpolated_inputRob Clark2019-07-026-0/+193
* panfrost: Pass referenced BOs to the SUBMIT ioctlsBoris Brezillon2019-07-021-19/+27
* panfrost: Make SLAB pool creation rely on BO helpersBoris Brezillon2019-07-027-110/+56
* panfrost: Add the panfrost_drm_{create,release}_bo() helpersBoris Brezillon2019-07-023-29/+70
* panfrost: Move the mmap BO logic out of panfrost_drm_import_bo()Boris Brezillon2019-07-021-21/+30
* panfrost: Avoid passing winsys handles to import/export BO funcsBoris Brezillon2019-07-023-19/+20
* panfrost: Move BO meta-data out of panfrost_boBoris Brezillon2019-07-026-94/+98
* panfrost: Stop exposing internal panfrost_drm_*() functionsBoris Brezillon2019-07-022-7/+2
* panfrost: Get rid of the "free imported BO" logicBoris Brezillon2019-07-024-37/+8
* panfrost: Get rid of the panfrost_driver abstraction leftoversBoris Brezillon2019-07-023-35/+0
* panfrost: Move scanout res creation out of panfrost_resource_create()Boris Brezillon2019-07-021-32/+41
* panfrost: Add the sampled texture BO to the jobBoris Brezillon2019-07-021-0/+4
* radv: enable DCC for layers on GFX8Samuel Pitoiset2019-07-021-9/+23
* radv: do not enable DCC for mipmapped arrays because performance is worseSamuel Pitoiset2019-07-021-0/+4
* radv: implement clearing DCC layers on GFX8Samuel Pitoiset2019-07-022-4/+7
* radv: merge radv_dcc_clear_level() into radv_clear_dcc()Samuel Pitoiset2019-07-021-30/+22
* radv: add support for decompressing DCC layers with computeSamuel Pitoiset2019-07-021-51/+53
* ac: compute the DCC fast clear size per slice on GFX8Samuel Pitoiset2019-07-022-0/+28
* ac: compute the size of one DCC slice on GFX8Samuel Pitoiset2019-07-022-0/+7
* iris: Defer closing and freeing VMA until buffers are idle.Kenneth Graunke2019-07-021-10/+51
* iris: Add an explicit alignment parameter to iris_bo_alloc_tiled().Kenneth Graunke2019-07-023-12/+19
* v3d: do not flush jobs that are synced with 'Wait for transform feedback'Iago Toral Quiroga2019-07-025-20/+61
* v3d: emit 'Wait for transform feedback' commands when neededIago Toral Quiroga2019-07-021-0/+120
* v3d: keep track of resources written by transform feedbackIago Toral Quiroga2019-07-023-2/+15
* st/dri: fix typo in format table for GR1616 formatMike Blumenkrantz2019-07-011-1/+1
* st/dri: pass dri2_format_mapping directly to dri2_create_image_from_winsysMike Blumenkrantz2019-07-011-4/+5
* mesa/st: simplify format usage in st_bind_egl_imageMike Blumenkrantz2019-07-011-15/+13
* iris: Use MI_COPY_MEM_MEM for tiny resource_copy_region calls.Kenneth Graunke2019-07-011-0/+27
* radv: Only allocate supplied number of descriptors when variable.Bas Nieuwenhuizen2019-07-011-1/+7
* egl: simplify loopEric Engestrom2019-07-011-3/+1
* sparc: Reuse m_vector_asm.h.Eric Anholt2019-07-013-34/+14
* mesa: Enable asm unconditionally, now that gen_matypes is gone.Eric Anholt2019-07-012-4/+0
* mesa: Replace gen_matypes with a simple header for V4F/mat layout.Eric Anholt2019-07-0126-270/+101
* matypes: Drop some unused defines.Eric Anholt2019-07-011-113/+0
* meson: drop duplicate source & inc_dirEric Engestrom2019-07-011-2/+0
* swrast: simplify function pointer callsEric Engestrom2019-07-012-3/+3
* egl/wayland: use bitset.h for `formats` bit setEric Engestrom2019-07-012-11/+19
* intel/tools: Add assembler unit tests for ROL/ROR instructionsSagar Ghuge2019-07-015-0/+5
* intel/tools: Add ROL/ROR support in assemblerSagar Ghuge2019-07-012-0/+10
* nir: Add lower_rotate flag and set to true in all driversSagar Ghuge2019-07-019-0/+11
* intel/compiler: Emit ROR and ROL instructionSagar Ghuge2019-07-012-0/+9
* nir: Add optimization to use ROR/ROL instructionsSagar Ghuge2019-07-012-0/+15
* nir: Add urol and uror opcodesSagar Ghuge2019-07-011-0/+11
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