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* mesa: add support for GL_INTEL_conservative_rasterizationLionel Landwerlin2016-12-0713-7/+129
* i965: Add i965 plumbing for ARB_post_depth_coverage for i965 (gen9+).Plamena Manolova2016-12-074-3/+13
* mesa: Add GL and GLSL plumbing for ARB_post_depth_coverage for i965 (gen9+).Plamena Manolova2016-12-0711-1/+53
* radeonsi: fix isolines tess factor writes to control ringNicolai Hähnle2016-12-071-4/+12
* i965: Drop redundant key->outputs_written initialization.Kenneth Graunke2016-12-061-2/+0
* i965: Initialize "separate" flag in VUE maps.Kenneth Graunke2016-12-061-0/+3
* nir: In split_var_copies_block, uint, int, and bool types cannot be matricesIan Romanick2016-12-061-3/+5
* radeonsi: Use amdgcn intrinsics for fs interpolationTom Stellard2016-12-071-54/+142
* freedreno/a5xx: fix draw packet size with index bufferRob Clark2016-12-061-1/+1
* freedreno/a5xx: gmem bypass modeRob Clark2016-12-061-0/+72
* freedreno/a5xx: fix emit_string_marker()Rob Clark2016-12-061-1/+4
* freedreno: pitch alignment should match gmem alignmentRob Clark2016-12-065-15/+22
* freedreno/a5xx: more formatsRob Clark2016-12-061-41/+41
* freedreno/a5xx: fix fragfaceRob Clark2016-12-061-2/+4
* freedreno/a5xx: fix fragcoordRob Clark2016-12-061-4/+11
* freedreno: update generated headersRob Clark2016-12-067-20/+129
* freedreno/a5xx: fix alpha testRob Clark2016-12-063-5/+1
* freedreno/a5xx: fix VPC_VAR[n].DISABLE bitsRob Clark2016-12-061-13/+13
* anv/TODO: Document sampling from HiZNanley Chery2016-12-061-0/+1
* i965: Don't force SSO layout for VS->TCS.Kenneth Graunke2016-12-062-4/+3
* i965: Unify shader interfaces explicitly.Kenneth Graunke2016-12-061-0/+29
* genxml/gen9: Change the default of MI_SEMAPHORE_WAIT::RegisterPoleModeJason Ekstrand2016-12-061-1/+1
* gallivm: optimize 16bit->32bit gather path a bitRoland Scheidegger2016-12-061-3/+39
* gallivm: handle 16bit float fetches in lp_build_fetch_rgba_soaRoland Scheidegger2016-12-061-4/+18
* util: (trivial) ETC1 meets the criteria for fitting into unorm8Roland Scheidegger2016-12-061-0/+5
* i965: Emit proper NOPs.Matt Turner2016-12-061-4/+2
* glsl: (trivial) fix type typoRoland Scheidegger2016-12-061-1/+1
* i965: Allocate at least some URB space even when max_vertices = 0.Kenneth Graunke2016-12-051-1/+7
* main: allow NEAREST_MIPMAP_NEAREST for stencil texturingRoland Scheidegger2016-12-061-15/+8
* glsl: fix ldexp lowering if bitfield insert lowering is also requestedRoland Scheidegger2016-12-061-5/+16
* radv: fix resource leak in radv_amdgpu_ctx_createNayan Deshmukh2016-12-061-0/+1
* st/omx/enc Raise default encode levelAndy Furniss2016-12-051-1/+1
* radeon/vce Handle H.264 level 5.2Andy Furniss2016-12-051-1/+2
* nir: Remove some unused fields from nir_variableJason Ekstrand2016-12-053-43/+0
* nir: Delete most of the constant_initializer supportJason Ekstrand2016-12-055-146/+12
* nir: Simplify nir_lower_gs_intrinsicsJason Ekstrand2016-12-051-21/+16
* nir/lower_returns: Stop using constant initializersJason Ekstrand2016-12-051-4/+5
* glsl/nir: Call nir_lower_constant_initializersJason Ekstrand2016-12-051-0/+2
* anv/pipeline: Call nir_lower_constant_initializersJason Ekstrand2016-12-051-0/+13
* nir: Add a pass for lowering away constant initializersJason Ekstrand2016-12-053-0/+115
* Revert "i965: use nir_lower_indirect_derefs() for GLSL"Jason Ekstrand2016-12-053-10/+23
* i965: Delete the meta-base CopyImageSubData implementationJason Ekstrand2016-12-054-328/+0
* i965/copy_image: Re-implement the blitter path with emit_miptree_blitJason Ekstrand2016-12-053-97/+80
* i965/blit: Break the guts of intel_miptree_blit into a helperJason Ekstrand2016-12-051-67/+84
* i965: use nir_lower_indirect_derefs() for GLSLTimothy Arceri2016-12-053-23/+10
* swr: mark PIPE_CAP_NATIVE_FENCE_FD unsupportedTim Rowley2016-12-051-0/+1
* swr: include llvm version and vector width in renderer stringTim Rowley2016-12-051-1/+11
* gallivm: use getHostCPUFeatures on x86/llvm-4.0+.Tim Rowley2016-12-051-0/+15
* st/va: declare vlVaBuffer before vlVaContextJuan A. Suarez Romero2016-12-051-15/+15
* st/va: remove unused variable pbuffJuan A. Suarez Romero2016-12-051-1/+0
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