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* util: rename PIPE_ARCH_*_ENDIAN to UTIL_ARCH_*_ENDIANDylan Baker2019-11-0549-122/+122
| | | | | | | | | | | As requested by Tim. This was generated with: grep 'PIPE_ARCH_.*_ENDIAN' -rIl | xargs sed -ie 's@PIPE_ARCH_\(.*\)_ENDIAN@UTIL_ARCH_\1_ENDIAN@'g v2: - add this patch Reviewed-by: Eric Engestrom <[email protected]>
* gallium/osmesa: Use PIPE_ARCH_*_ENDIAN instead of little_endian functionDylan Baker2019-11-051-20/+15
| | | | Reviewed-by: Eric Engestrom <[email protected]>
* mesa/main: delete now unused _mesa_little_endianDylan Baker2019-11-051-12/+0
| | | | Reviewed-by: Eric Engestrom <[email protected]>
* mesa/swrast: replace instances of _mesa_little_endian with preprocessorDylan Baker2019-11-052-6/+5
| | | | Reviewed-by: Eric Engestrom <[email protected]>
* mesa/main: replace uses of _mesa_little_endian with preprocessorDylan Baker2019-11-056-21/+49
| | | | Reviewed-by: Eric Engestrom <[email protected]>
* util/u_endian: set PIPE_ARCH_*_ENDIAN to 1Dylan Baker2019-11-0541-104/+100
| | | | | | | | | | | | This will allow it to be used as a drop in replacement for _mesa_little_endian in a number of cases. v2: - Always define PIPE_ARCH_LITTLE_ENDIAN and PIPE_ARCH_BIG_ENDIAN, define the one that reflects the host system to 1 and the other to 0 - replace all uses of #ifdef, #ifndef, and #if defined() with #if and #if ! with PIPE_ARCH_*_ENDIAN Reviewed-by: Eric Engestrom <[email protected]>
* util/u_endian: Use _WIN32 instead of _MSC_VERDylan Baker2019-11-051-1/+1
| | | | | | | | | _WIN32 is defined by basically all windows compilers (MSVC, ICL, MinGW), wereas _MSC_VER is not defined by MinGW. Without this change MinGW falls through and doesn't define PIPE_ARCH at all, and is caught by some extra code in gallium. Reviewed-by: Eric Engestrom <[email protected]>
* dri/osmesa: use preprocessor for selecting endian code pathsDylan Baker2019-11-051-6/+9
| | | | Reviewed-by: Eric Engestrom <[email protected]>
* r100: Use preprocessor to select big vs little endian pathsDylan Baker2019-11-053-46/+51
| | | | Reviewed-by: Eric Engestrom <[email protected]>
* r200: use preprocessor for big vs little endian checksDylan Baker2019-11-052-45/+38
| | | | | | | Instead of using a function at runtime we can just build the right code for the right platform. Reviewed-by: Eric Engestrom <[email protected]>
* svga: check return value of define_query_vgpu{9,10}Philipp Sieweck2019-11-051-8/+23
| | | | Reviewed-by: Charmaine Lee <[email protected]>
* mesa: add EXT_dsa glGetVertexArray* 4 functionsPierre-Eric Pelloux-Prayer2019-11-055-4/+309
| | | | | | | | | | | | The implementation doesn't share much with get.c because: * the refactoring needed for get.c to not depend on ctx->Array.VAO would be quite large * glGetVertexArray* would still need to filter pname to only accept the one specified by the spec * these functions are getter, the implementation is trivial (the complexity is in the correct filtering of pname input) Reviewed-by: Marek Olšák <[email protected]>
* mesa: extract helper function from _mesa_GetPointervPierre-Eric Pelloux-Prayer2019-11-052-29/+47
| | | | | | Will be used by EXT_dsa gllGetVertexArrayPointervEXT implementation. Reviewed-by: Marek Olšák <[email protected]>
* mesa: add EXT_dsa EnableVertexArrayAttribEXT / DisableVertexArrayAttribEXTPierre-Eric Pelloux-Prayer2019-11-055-2/+50
| | | | Reviewed-by: Marek Olšák <[email protected]>
* mesa: add EXT_dsa glEnableVertexArrayEXT / glDisableVertexArrayEXTPierre-Eric Pelloux-Prayer2019-11-055-2/+81
| | | | Reviewed-by: Marek Olšák <[email protected]>
* mesa: add gl_vertex_array_object parameter to client state helpersPierre-Eric Pelloux-Prayer2019-11-051-22/+25
| | | | | | | This will allow to use the same helper for the EXT_direct_state_access implementation. Reviewed-by: Marek Olšák <[email protected]>
* mesa: add EXT_dsa glVertexArray* functions implementationPierre-Eric Pelloux-Prayer2019-11-051-0/+308
| | | | Reviewed-by: Marek Olšák <[email protected]>
* mesa: add vao/vbo lookup helper for EXT_dsaPierre-Eric Pelloux-Prayer2019-11-051-0/+32
| | | | | | | | Add a single helper dealing with the lookup of both the vao and the vbo to avoid duplicating this code in all the glVertexArray* functions. Reviewed-by: Marek Olšák <[email protected]>
* mesa: rework _mesa_lookup_vao_err to allow usage from EXT_dsaPierre-Eric Pelloux-Prayer2019-11-053-18/+36
| | | | | | | | | ARB_dsa and EXT_dsa slightly differs when an uninitialized VAO is requested. In this case ARB_dsa fails while EXT_dsa requires to initialize the object. Reviewed-by: Marek Olšák <[email protected]>
* mesa: add EXT_dsa glVertexArray* functions declarationsPierre-Eric Pelloux-Prayer2019-11-055-11/+257
| | | | Reviewed-by: Marek Olšák <[email protected]>
* mesa: pass vao as a function paramterPierre-Eric Pelloux-Prayer2019-11-051-60/+94
| | | | | | | This change will allow reusing the same function for the EXT_direct_state_access implementation. Reviewed-by: Marek Olšák <[email protected]>
* nir: Handle image arrays when setting variable dataKenneth Graunke2019-11-041-1/+1
| | | | | | | Fixes a ton of regressions in image load store tests. Fixes: 4319cc8c0f5 ("nir: pack nir_variable::data::xfb_*") Acked-by: Alyssa Rosenzweig <[email protected]>
* intel/compiler: remove the operand restriction for src1 on GLKPaulo Zanoni2019-11-051-2/+1
| | | | | | | | | | | | | | | | | | | | | | | | Commit 5847de6e9afe implemented a restriction that applies to ICL, but wrongly marked it as also applying to GLK. Reviewers or MR !1125 pointed this, and the commit history shows removal of GLK to parts of the patch, but it turns there was still a left-over GLK check in the code. This code was breaking some of the i8vec2 tests on GLK, for example: dEQP-VK.subgroups.arithmetic.compute.subgroupadd_i8vec2 Removing the GLK check solves the issue for GLK. I don't see a reason on why implementing this restriction would actually break GLK, so there's still more to investigate here since this bug may be affecting ICL+, but let's apply the real GLK fix while we analyze and discuss the other possible issues. Fixes: 5847de6e9afe ("intel/compiler: don't use byte operands for src1 on ICL") BSpec: 3017 Reviewed-by: Lionel Landwerlin <[email protected]> Reviewed-by: Matt Turner <[email protected]> Signed-off-by: Paulo Zanoni <[email protected]>
* nir: pack nir_variable::data::xfb_*Marek Olšák2019-11-044-31/+38
| | | | Reviewed-by: Connor Abbott <[email protected]>
* nir: pack nir_variable::data::streamMarek Olšák2019-11-043-5/+8
| | | | Reviewed-by: Connor Abbott <[email protected]>
* nir/algebraic: Mark other comparison exact when removing a == aIan Romanick2019-11-041-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This prevents some additional optimizations that would change the original result. This includes things like (b < a && b < c) => b < min(a, c) and !(a < b) => b >= a. Both of these optimizations were specifically observed in the piglit tests added in piglit!160. This was discovered while investigating https://gitlab.freedesktop.org/mesa/mesa/issues/1958. However, the problem in that issue was Chrome or Angle is replacing calls to isnan() with some stuff that we (correctly) optimize to false. If they had left the calls to isnan() alone, everything would have just worked. No shader-db changes on any Intel platform. I also tried marking the comparison generated by the isnan() function precise. The precise marker "infects" every computation involved in calculating the parameter to the isnan() function, and this severely hurt all of the (few) shaders in shader-db that use isnan(). I also considered adding a new ir_unop_isnan opcode that would implement the functionality. During GLSL IR-to-NIR translation, the resulting comparison operation would be marked exact (and the samething would need to happen in SPIR-V translation). This approach taken by this patch seemed easier, but we may want to do the ir_unop_isnan thing anyway. Fixes: d55835b8bdf ("nir/algebraic: Add optimizations for "a == a && a CMP b"") Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Connor Abbott <[email protected]>
* nir/algebraic: Add the ability to mark a replacement as exactIan Romanick2019-11-044-3/+13
| | | | | Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Connor Abbott <[email protected]>
* compiler: make variable::data::binding unsignedMarek Olšák2019-11-042-2/+2
| | | | | | Nothing seems to set a negative value. Reviewed-by: Connor Abbott <[email protected]>
* st/mesa: call nir_lower_flrp only once per shaderMarek Olšák2019-11-042-16/+22
| | | | Reviewed-by: Connor Abbott <[email protected]>
* st/mesa: call nir_opt_access only onceMarek Olšák2019-11-042-2/+2
| | | | Reviewed-by: Connor Abbott <[email protected]>
* ac: add missing Arcturus to the info of pc linesLeo Liu2019-11-041-0/+2
| | | | | | Signed-off-by: Leo Liu <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Cc: Marek Olšák <[email protected]>
* pan/midgard: Extend default_phys_reg to !32-bitAlyssa Rosenzweig2019-11-041-5/+5
| | | | | | We can pass through a size. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* pan/midgard: Extend swizzle packing for vec4/16-bitAlyssa Rosenzweig2019-11-041-3/+24
| | | | | | | | We would like to pack not just xyzw swizzles but also efgh swizzles. This should work for vec4/16-bit. More work will be needed to pack swizzles for vec8/16-bit and even more work for 8-bit, of course. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* pan/midgard: Extend offset_swizzle to non-32-bitAlyssa Rosenzweig2019-11-041-3/+4
| | | | | | We take a size parameter; use it. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* pan/midgard: offset_swizzle doesn't need dstsizeAlyssa Rosenzweig2019-11-041-9/+9
| | | | | | This argument should be omitted. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* pan/midgard: Add bizarre corner caseAlyssa Rosenzweig2019-11-041-1/+8
| | | | | | Someone really needs to look into this. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* pan/midgard: Compute bundle interferenceAlyssa Rosenzweig2019-11-041-0/+57
| | | | Signed-off-by: Alyssa Rosenzweig <[email protected]>
* pan/midgard: Fix quadword_count handlingAlyssa Rosenzweig2019-11-043-4/+8
| | | | | | Spilling can mess with this considerably. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* pan/midgard: Validate tags when branchingAlyssa Rosenzweig2019-11-041-6/+32
| | | | | | | | | | | | | | | | | | Midgard prefetches instructions based on tag (ALU, LD/ST, texture * size). To do so, the shader descriptor specifies the tag of the first instruction, all instructions specify the tag of the next linear instruction is, and all branches explicitly specify the tag of the branch target. If you mess this up, you get an INSTR_TYPE_MISMATCH, which unambiguously refers to this problem, but it's still annoying to try to work out all the branch targets in your head to debug. Instead, let's track the tags of various blocks over time, so we can automatically validate tags of branch targets, to make INSTR_TYPE_MISMATCH issues immediately obvious in a disassembly. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* aco: fix accidential reordering of instructions when schedulingDaniel Schürmann2019-11-041-10/+47
| | | | | | Fixes: 86786999189c43b4a2c8e1c1a18b55cd2f369fff "aco: implement VGPR spilling" Reviewed-by: Rhys Perry <[email protected]>
* aco: only use single-dword loads/stores for spillingDaniel Schürmann2019-11-041-41/+10
| | | | | | Fixes: 86786999189c43b4a2c8e1c1a18b55cd2f369fff "aco: implement VGPR spilling" Reviewed-by: Rhys Perry <[email protected]>
* aco: fix immediate offset for spills if scratch is usedDaniel Schürmann2019-11-041-6/+6
| | | | | | Fixes: 86786999189c43b4a2c8e1c1a18b55cd2f369fff "aco: implement VGPR spilling" Reviewed-by: Rhys Perry <[email protected]>
* anv: Properly handle host query reset of performance queriesLionel Landwerlin2019-11-041-32/+20
| | | | | | | | | | | | The host query reset entry point didn't use the availability offset for performance queries. To fix this, reorder the availability of performance queries to match other queries. Signed-off-by: Lionel Landwerlin <[email protected]> Fixes: 2b5f30b1d9 ("anv: implement VK_INTEL_performance_query") Reviewed-by: Jason Ekstrand <[email protected]>
* state_tracker: Handle texture view min level in st_generate_mipmap()Paul Gofman2019-11-041-1/+7
| | | | | Signed-off-by: Paul Gofman <[email protected]> Signed-off-by: Marek Olšák <[email protected]>
* iris: try to set the specified tiling when importing a dmabufJames Xiong2019-11-043-11/+29
| | | | | | | | | | | | | | | | | | When importing a dmabuf with a specified tiling, the dmabuf user should always try to set the tiling mode because: 1) the exporter can set tiling AFTER exporting/importing. 2) a dmabuf could be exported from a kernel driver other than i915, in this case the dmabuf user and exporter need to set tiling separately. This patch fixes a problem when running vkmark under weston with iris on ICL, it crashed to console with the following assert. i965 doesn't have this problem as it always tries to set the specified tiling mode. weston: ../src/gallium/drivers/iris/iris_resource.c:990: iris_resource_from_handle: Assertion `res->bo->tiling_mode == isl_tiling_to_i915_tiling(res->surf.tiling)' failed. Signed-off-by: James Xiong <[email protected]> Reviewed-by: Rafael Antognolli <[email protected]>
* iris: Fix "Force Zero RTA Index Enable" setting againKenneth Graunke2019-11-041-1/+1
| | | | | | | | | | In 2ca0d913ea8, we began updating cso_fb->layers to the actual layer count, rather than 0. This fixed cases where we were setting "Force Zero RTA Index Enable" even when doing layered rendering. Sadly, it also broke the check entirely: cso_fb->layers is now 1 for non-layered cases, but the Force Zero RTA Index check was still comparing for 0. Fixes: 2ca0d913ea8 ("iris: Fix framebuffer layer count")
* nir: correct use of identity check in pythonDylan Baker2019-11-041-2/+2
| | | | | | | | | | Python has the identity operator `is`, and the equality operator `==`. Using `is` with strings sometimes works in CPython due to optimizations (they have some kind of cache), but it may not always work. Fixes: 96c4b135e34d0804e41bfbc28fc1b5050c49d71e ("nir/algebraic: Don't put quotes around floating point literals") Reviewed-by: Matt Turner <[email protected]>
* panfrost: MALI_DEPTH_TEST is actually MALI_DEPTH_WRITEMASKBoris Brezillon2019-11-043-4/+5
| | | | | | | | | MALI_DEPTH_TEST should only be set when depth->writemask is true, not when the depth test is enabled. Let's rename the flag and patch panfrost_bind_depth_stencil_state() to do the right thing. Signed-off-by: Boris Brezillon <[email protected]> Reviewed-by: Alyssa Rosenzweig <[email protected]>
* vulkan: bump headers/registry to 1.1.127Lionel Landwerlin2019-11-041-4/+49
| | | | | Signed-off-by: Lionel Landwerlin <[email protected]> Acked-by: Jason Ekstrand <[email protected]>
* radv: fix compute pipeline keys when optimizations are disabledSamuel Pitoiset2019-11-041-2/+18
| | | | | | | | | | | If an app first creates a compute pipeline with VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT set, then re-compile it without that flag, the driver should re-compile the compute shader. Otherwise, it will return the unoptimized one. Fixes: ce188813bfe ("radv: add initial support for VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT") Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
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