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* freedreno/ir3: lower extract_byte/wordRob Clark2016-03-131-0/+2
| | | | | | | | | | | | | | | | | | | | | | | The following commits broke things by starting to feed us unhandled extract_u16/extract_u8 opcodes: commit 905ff861982450831a56d112036f68a751337441 Author: Matt Turner <[email protected]> AuthorDate: Wed Feb 3 14:28:31 2016 -0800 Commit: Matt Turner <[email protected]> CommitDate: Fri Mar 4 11:52:34 2016 -0800 nir: Recognize open-coded extract_u16. commit 76289fbfa84a06ef4db8ad44ea0eb88ad0be8d5c Author: Matt Turner <[email protected]> AuthorDate: Thu Jan 21 09:09:48 2016 -0800 Commit: Matt Turner <[email protected]> CommitDate: Fri Mar 4 11:52:34 2016 -0800 nir: Recognize open-coded extract_u8. Signed-off-by: Rob Clark <[email protected]>
* nv50,nvc0: handle SQRT lowering inside the driverIlia Mirkin2016-03-136-23/+27
| | | | | | | | | | | | | | | | | | | | | First off, st/mesa lowers DSQRT incorrectly (it uses CMP to attempt to find out whether the input is less than 0). Secondly the current approach (x * rsq(x)) behaves poorly for x = inf - a NaN is produced instead of inf. Instead we switch to the less accurate rcp(rsq(x)) method - this behaves nicely for all valid inputs. We still don't do this for DSQRT since the RSQ/RCP ops are *really* inaccurate, and don't even have Newton-Raphson steps right now. Eventually we should have a separate library function for DSQRT that does it more precisely (and perhaps move this lowering to the post-opt phase). This fixes a number of dEQP precision tests that were expecting better behavior for infinite inputs. Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]> Tested-by: Samuel Pitoiset <[email protected]>
* nv50/ir: avoid folding mul + add if the mul has a dnzIlia Mirkin2016-03-131-3/+2
| | | | | Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]>
* nvc0: fix blit triangle size to fully cover FB's > 8192x8192Ilia Mirkin2016-03-131-4/+4
| | | | | | | | | | | | | | The idea is that a single triangle will cover the whole area being drawn, allowing the blit shader to do its work. However the max fb size is 16384x16384, which means that the triangle we draw needs to be twice that in order to cover the whole area fully. Increase the size of the triangle to 32768x32768. This fixes a number of dEQP tests that were failing because a blit was involved which would miss some of the resulting texture. Signed-off-by: Ilia Mirkin <[email protected]> Cc: "11.1 11.2" <[email protected]>
* freedreno: OUT_RELOC vs OUT_RELOCW fixesRob Clark2016-03-133-7/+7
| | | | | | Make sure we use OUT_RELOCW() in cases where the buffer is written to. Signed-off-by: Rob Clark <[email protected]>
* freedreno/a4xx: hw binningRob Clark2016-03-134-33/+210
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/a4xx: use generated headers for draw initiatorRob Clark2016-03-131-3/+4
| | | | | | No need to open-code this. Signed-off-by: Rob Clark <[email protected]>
* freedreno/a4xx: remove RB_RENDER_CONTROL patchingRob Clark2016-03-136-41/+8
| | | | | | | | | Bitfields where shuffled around for the better on a4xx, so we don't need any patching on this one. It appears to be something we set entirely in the gmem code so no conflict between tiling and render state like we had in a3xx. Signed-off-by: Rob Clark <[email protected]>
* freedreno: update generated headersRob Clark2016-03-135-11/+32
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/a3xx: move where we deal w/ binning FSRob Clark2016-03-133-10/+10
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/a4xx: move where we deal w/ binning FSRob Clark2016-03-133-10/+10
| | | | | | | Move where we pick dummy FS for binning pass, so the whole driver sees the same dummy/no-op FS stage. Signed-off-by: Rob Clark <[email protected]>
* freedreno/a3xx: constify the shader variantsRob Clark2016-03-132-6/+6
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/a4xx: constify the shader variantsRob Clark2016-03-134-13/+13
| | | | | | Most of the driver just needs read-only access, so constify.. Signed-off-by: Rob Clark <[email protected]>
* freedreno/a3xx: remove duplicate mark of end of binning cmdsRob Clark2016-03-131-3/+0
| | | | Signed-off-by: Rob Clark <[email protected]>
* radeonsi: avoid crash when a sampler state is bound for a buffer textureNicolai Hähnle2016-03-131-0/+1
| | | | | | | | | | | | | Sampler states don't really make sense with buffer textures, but they can be set anyway, so we need to be defensive here. This bug was lurking for a while and was finally noticed due to PBO uploads setting sampler states. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=94284 Cc: [email protected] Reviewed-by: Marek Olšák <[email protected]> Tested-by: Laurent Carlier <[email protected]> Tested-by: Shawn Starr <[email protected]>
* i965: Use foreach_in_list_reverse_safe() macro.Matt Turner2016-03-121-12/+2
| | | | Reviewed-by: Ian Romanick <[email protected]>
* nir/clone: Add support for cloning a single function_implJason Ekstrand2016-03-122-32/+81
| | | | Reviewed-by: Jordan Justen <[email protected]>
* nir/validate: Better function validationJason Ekstrand2016-03-121-7/+15
| | | | Reviewed-by: Jordan Justen <[email protected]>
* nir/print: Better function argument printingJason Ekstrand2016-03-121-2/+10
| | | | | | | | Since we aren't going to put the function parameters or the return variable in the list of locals, it won't get a proper declaration. This changes nir_print to print the type along with each parameter or return variable. Reviewed-by: Jordan Justen <[email protected]>
* nir/print: Factor variable name lookup into a helperJason Ekstrand2016-03-121-30/+36
| | | | | | | | Otherwise, we have a problem when we go to print functions with arguments because their names get added to the hash table during declaration which happens after we print the prototype. Reviewed-by: Jordan Justen <[email protected]>
* nir: Create function parameters in function_impl_createJason Ekstrand2016-03-121-0/+20
| | | | Reviewed-by: Jordan Justen <[email protected]>
* nir: Add a helper for creating a "bare" nir_function_implJason Ekstrand2016-03-122-10/+20
| | | | Reviewed-by: Jordan Justen <[email protected]>
* nir: Add a new "param" variable mode for parameters and return variablesJason Ekstrand2016-03-123-2/+13
| | | | Reviewed-by: Jordan Justen <[email protected]>
* nir/glsl: Remove dead function parameter handling codeJason Ekstrand2016-03-121-46/+5
| | | | | | | | | NIR has never been used on IR where we haven't already done function inlining so this code has been dead from the beginning. Let's just get rid of it for now. We can always put it back in if we decide to use NIR for function inlining at some point in the future. Reviewed-by: Jordan Justen <[email protected]>
* st/va: add HEVC main 10 profileBoyuan Zhang2016-03-111-1/+4
| | | | | | Signed-off-by: Boyuan Zhang <[email protected]> Reviewed-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]>
* radeon/video: enable HEVC main 10 decodeBoyuan Zhang2016-03-111-2/+6
| | | | | | Signed-off-by: Boyuan Zhang <[email protected]> Reviewed-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]>
* radeon/uvd: handle HEVC main 10 decodeBoyuan Zhang2016-03-111-11/+58
| | | | | Signed-off-by: Boyuan Zhang <[email protected]> Reviewed-by: Alex Deucher <[email protected]>
* i965/chv: Display proper brandingBen Widawsky2016-03-113-5/+31
| | | | | | | | | | | | | | | | | | | | | | "Braswell" is a Cherryview based *thing*. It unfortunately requires extra information to determine its marketing name. Unlike all previous products, and hopefully all future ones, there is no unique 1:1 mapping of PCI device ID to brand string. I put up a fight about adding any complexity to our GL renderer string code for a very long time. However, a wise man made a comment to me that I couldn't argue with: if a user installs Windows on their hardware, the brand string should be the same as what we display in Linux. The Windows driver apparently does this check, so we should too. Note that I did manage to find a good use for this info anyway in the compute shader thread counts. v2: memcpy instead of strncpy, and some minor changes (Matt) Signed-off-by: Ben Widawsky <[email protected]> Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Jordan Justen <[email protected]
* i965/chv: Update lower min for CS threadsBen Widawsky2016-03-111-1/+1
| | | | | | | | We have better information now, and 28 was not a valid thing to support. 6 EUs per sublice with 7 threads per EU is the minimum supported config. Signed-off-by: Ben Widawsky <[email protected]> Reviewed-by: Jordan Justen <[email protected]
* i965/chv: Check that compute threads are above thresholdBen Widawsky2016-03-112-0/+9
| | | | | | | | | | | | | The way we are organizing this code, the statically configured max_cs_threads should always be the minimum value we actually support (ie. are aware of). As a result, we can fall back to that if we get invalid numbers from the kernel (ie. when the query succeeds, but the result is lower than expected). I was originally planning to use an assert, but there is no reason to be so mean. Signed-off-by: Ben Widawsky <[email protected]> Reviewed-by: Jordan Justen <[email protected]
* i965/chv: Use kernel provided info for max_cs_threadsBen Widawsky2016-03-111-1/+8
| | | | | | | | | | | | | With the previous patches, the code can find out the actual number of available compute threads. It is enabled only for Cherryview since that is the only platform I know for a fact has shipped devices which can benefit from this. It seems like other platforms /might/ benefit from this because of fused configurations which /might/ have shipped. Fallback code is still there. v2: Some minor adjustments from Matt Signed-off-by: Ben Widawsky <[email protected]> Reviewed-by: Jordan Justen <[email protected]
* i965: Query and store GPU properties from kernelBen Widawsky2016-03-112-1/+31
| | | | | | | | | | | | | | | | | Certain products are not uniquely identifiable based on device id alone. The kernel exports an interface to help deal with this. This patch merely introduces the consumer of the interface and makes sure nothing breaks. It is also possible to use these values for programming GPGPU mode, and I plan to do that as well. The interface was introduced in libdrm 2.4.60, which is already required, so it should all be fine. v2: Some minor changes recommended by Matt Signed-off-by: Ben Widawsky <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* st/mesa: check that the image unit is valid in st_bind_imagesNicolai Hähnle2016-03-111-1/+2
| | | | Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: Lazily re-set sampler views after disabling DCCBas Nieuwenhuizen2016-03-112-5/+8
| | | | | | | | | | Clear DCC flags if necessary when binding a new sampler view. v2: Do not reset DCC flags of bound sampler views. v3: Check that we have a real texture (Nicolai) Signed-off-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* st/mesa: remove ST_NEW_MESA flag (v2)Marek Olšák2016-03-114-6/+4
| | | | | | | | Only used indirectly when checking dirty.st != 0 v2: also update st_cb_compute.c Reviewed-by: Ilia Mirkin <[email protected]>
* r600g: clear compressed_depthtex/colortex_mask when binding buffer textureNicolai Hähnle2016-03-111-12/+12
| | | | | | | | | | | Found by inspection of the source based on a bisected bug report. This bug has been in the code for a long time, but the more recent PBO upload feature exposed it because it leads to more uses of buffer textures. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=94388 Reviewed-by: Marek Olšák <[email protected]> Cc: "11.0 11.1 11.2" <[email protected]>
* st/mesa: add GL_ARB_shader_atomic_counter_ops supportIlia Mirkin2016-03-102-7/+57
| | | | | Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* mesa: add GL_ARB_shader_atomic_counter_ops supportIlia Mirkin2016-03-106-0/+118
| | | | | Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* nvc0: add support for TGSI FMA opsIlia Mirkin2016-03-102-1/+7
| | | | | | | | This will allow the nouveau backend to not try and split up ops that are fused in GLSL. Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]>
* radeonsi: update compressed_colortex_masks when a cmask is created or disabledNicolai Hähnle2016-03-103-2/+51
| | | | | Reviewed-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: move si_decompress_textures to si_blit.cNicolai Hähnle2016-03-103-23/+23
| | | | | | | | | Since it is all about calling into blitter functions, it makes more sense here. This change also reduces the size of the interfaces between .c files. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* r600g: update compressed_colortex_masks when a cmask is created or disabledNicolai Hähnle2016-03-101-0/+30
| | | | | Reviewed-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* gallium/radeon: notify all contexts when cmasks are enabled/disabledNicolai Hähnle2016-03-102-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | There is an annoying corner case that I stumbled across while looking into piglit's arb_shader_image_load_store/execution/load-from-cleared-image.shader_test (which can be easily adapted to demonstrate the bug without the ARB_shader_image_load_store extension) When we bind a texture and then clear it using glClear (by attaching it to the current framebuffer) for the first time, we allocate a separate cmask for the texture to do fast clear, but the corresponding bit in compressed_colortex_mask is not set. Subsequent rendering will use incorrect data. Conversely, when a currently bound texture with an existing cmask is exported leading to that cmask being disabled, the compressed_colortex_mask bit will remain set, leading to an assertion later on in debug builds. Since iterating through all contexts and/or remembering where every texture is bound would be costly, and cmask enable/disable should be rare, we will maintain a global counter to signal contexts that they must update their compressed_colortex_masks. This patch introduces the global counter, and subsequent patches will do the mask update. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* i965: Set a proper _BaseFormat for window system renderbuffers in ES.Kenneth Graunke2016-03-101-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | intel_alloc_private_renderbuffer_storage did: rb->_BaseFormat = _mesa_base_fbo_format(ctx, internalFormat); Unfortunately, internalFormat was usually an unsized format (such as GL_DEPTH_COMPONENT). In OpenGL ES, _mesa_base_fbo_format() refuses to accept unsized formats, and returns 0 rather than a real base format. This meant that we ended up with a completely bogus rb->_BaseFormat for window system buffers on OpenGL ES. All other renderbuffer allocation functions in intel_fbo.c instead use the mesa_format, and do: rb->_BaseFormat = _mesa_get_format_base_format(...); We can do likewise, using rb->Format. This appears to work just fine. dEQP-GLES3.functional.state_query.fbo.framebuffer_attachment_x_size_initial failed, as it tried to perform a GL_FRAMEBUFFER_ATTACHMENT_DEPTH_SIZE query on the window system depth buffer. That query relies on a proper rb->_BaseFormat being set, so it broke because rb->_BaseFormat was 0 due to the above bug. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=94458 Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Iago Toral Quiroga <[email protected]>
* glcpp: Fix locations when encounting "#<NEWLINE>".Kenneth Graunke2016-03-102-1/+4
| | | | | | | | | | | | | | | We were failing to reset our location tracking when encountering a NEWLINE in the <HASH> state. Rip the code from the <*>{NEWLINE} rule, which handles this properly. Also, update 146-version-first-hash.c to have proper expectations. When I introduced the test, I didn't verify that the line/column numbers were correct, and it turns out they varied based on the type of newline ending. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=94447 Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Iago Toral Quiroga <[email protected]>
* gallium/swr: remove use of BYTE from swr driverTim Rowley2016-03-104-14/+14
| | | | | | Remove use of a win32-style type leaked from the swr rasterizer. Reviewed-by: Bruce Cherniak <[email protected]>
* nvc0: expose SM35 perf counters to AMD_performance_monitorSamuel Pitoiset2016-03-101-2/+2
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Acked-by: Ilia Mirkin <[email protected]>
* nvc0: add driver metrics for SM35 (GK110)Samuel Pitoiset2016-03-101-1/+20
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Acked-by: Ilia Mirkin <[email protected]>
* nvc0: add MP performance counters for SM35 (GK110)Samuel Pitoiset2016-03-103-17/+204
| | | | | | | | | Because compute support is not enabled by default for these chipsets, NVF0_COMPUTE=1 needs to be used, along with GALLIUM_HUD to enable performance counters. Signed-off-by: Samuel Pitoiset <[email protected]> Acked-by: Ilia Mirkin <[email protected]>
* nvc0: explode config of Kepler hardware SM eventsSamuel Pitoiset2016-03-101-78/+477
| | | | | | | | This is really verbose but most of the configuration will be reused for SM35 (GK110). Signed-off-by: Samuel Pitoiset <[email protected]> Acked-by: Ilia Mirkin <[email protected]>
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