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* mesa: remove 'params' parameter from ctx->Driver.TexParameter()Brian Paul2016-10-138-37/+20
* vc4: Avoid loading from the texture during non-utile-aligned glTexImage().Eric Anholt2016-10-131-12/+34
* st/nine: Fix possible segfault in surface ctorAxel Davy2016-10-131-2/+2
* st/nine: Remove useless code in nine_shaderAxel Davy2016-10-131-5/+0
* gallium/os: Use unsigned integers for size computationAxel Davy2016-10-131-2/+2
* nvc0: enable ARB_enhanced_layoutsSamuel Pitoiset2016-10-131-1/+1
* radv: fix the wayland wsi busy bitDave Airlie2016-10-141-1/+1
* anv: fix the wayland wsi busy flag settingDave Airlie2016-10-141-1/+1
* radv: Use new image load/store intrinsic signatures v2Tom Stellard2016-10-141-25/+108
* radv: Fix incorrect commentTom Stellard2016-10-141-2/+2
* radv: fix identity swizzle handlingDave Airlie2016-10-141-8/+10
* anv/wsi: fix apps that acquire multiple images up frontDave Airlie2016-10-142-0/+2
* radv/wsi: fix app that acquire multiple images up frontDave Airlie2016-10-142-0/+2
* anv: initialise and increment send_sbcDave Airlie2016-10-141-0/+2
* radeonsi: adjust and clean up Z_ORDER and EXEC_ON_x settingsMarek Olšák2016-10-132-22/+32
* radeonsi: disable ReZMarek Olšák2016-10-131-7/+4
* radeonsi: implement TC-compatible HTILEMarek Olšák2016-10-139-24/+185
* gallium: add PIPE_RESOURCE_FLAG_TEXTURING_MORE_LIKELYMarek Olšák2016-10-132-1/+3
* radeonsi: fix regression in image atomicsNicolai Hähnle2016-10-131-1/+1
* st/mesa: fix vertex elements setup for doublesNicolai Hähnle2016-10-131-48/+50
* st/glsl_to_tgsi: remove unnecessary ir_instruction argument from get_opcodeNicolai Hähnle2016-10-131-3/+3
* st/glsl_to_tgsi: fix textureGatherOffset with indirectly loaded offsetsNicolai Hähnle2016-10-131-1/+17
* st/glsl_to_tgsi: simplify translate_tex_offsetNicolai Hähnle2016-10-131-50/+14
* radeonsi: fix the coordinate overloading of llvm.amdgcn.image.atomic.cmpswap.*Nicolai Hähnle2016-10-131-2/+7
* radv: Return correct result in EnumeratePhysicalDevicesNicolas Koch2016-10-131-0/+2
* st/mesa: only flip stipple pattern for winsys fbo'sIlia Mirkin2016-10-121-3/+7
* swr: automake: add ar_eventhandlerfile_h.template to the tarballEmil Velikov2016-10-121-1/+2
* radv: add all headers to the sources listEmil Velikov2016-10-121-1/+12
* nvc0/ir: fix textureGather with a single offsetIlia Mirkin2016-10-121-2/+2
* nv50/ir: copy over value's register id when resolving merge of a phiIlia Mirkin2016-10-121-1/+3
* st/mesa: enable ARB_enhanced_layouts and turn the cap onNicolai Hähnle2016-10-124-3/+10
* st/glsl_to_tgsi: adjust swizzles and writemasks for explicit componentsNicolai Hähnle2016-10-121-19/+49
* st/glsl_to_tgsi: explicitly track all input and output declarationNicolai Hähnle2016-10-121-154/+171
* st/glsl_to_tgsi: mark "gaps" in input/output arrays as usedNicolai Hähnle2016-10-121-8/+24
* st/glsl_to_tgsi: disable on-the-fly peephole for 64-bit operationsNicolai Hähnle2016-10-121-0/+4
* st/glsl_to_tgsi: simpler fixup of empty writemasksNicolai Hähnle2016-10-121-27/+10
* st/glsl_to_tgsi: explicit handling of writemask for depth/stencil exportNicolai Hähnle2016-10-121-8/+17
* glsl: dump explicit location when printing IRNicolai Hähnle2016-10-121-3/+7
* tgsi/ureg: add ureg_DECL_output_layoutNicolai Hähnle2016-10-122-13/+38
* tgsi/ureg: add layout/component input declarationsNicolai Hähnle2016-10-122-12/+76
* tgsi/scan: fix num_inputs/num_outputs for shaders with overlapping arraysNicolai Hähnle2016-10-121-8/+2
* gallium: add PIPE_CAP_TGSI_ARRAY_COMPONENTSNicolai Hähnle2016-10-1217-0/+24
* radeonsi: Use the new image load/store intrinsic signaturesTom Stellard2016-10-121-14/+45
* radeonsi: Add function for converting LLVM type to intrinsic stringTom Stellard2016-10-121-10/+32
* radeonsi: Refactor image store/load intrinsic name creationTom Stellard2016-10-121-11/+18
* winsys/amdgpu: fix infinite loop w/ RADEON_NOOP=1 caused by unsubmitted fencesMarek Olšák2016-10-121-2/+5
* radeonsi: fix R600_DEBUG=precompile for shader-dbMarek Olšák2016-10-121-0/+6
* radeonsi: use TC write-back instead of full cache invalidationMarek Olšák2016-10-123-13/+7
* radeonsi: implement TC L2 write-back (flush) without cache invalidationMarek Olšák2016-10-122-28/+74
* radeonsi: don't invalidate VMEM L1 for memory barriers for index buffersMarek Olšák2016-10-121-3/+4
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