summaryrefslogtreecommitdiffstats
path: root/src
Commit message (Expand)AuthorAgeFilesLines
* vc4: Drop VS inputs to 8.Eric Anholt2017-02-101-4/+1
* vc4: Avoid emitting small immediates for UBO indirect load address guards.Eric Anholt2017-02-105-4/+20
* util/disk_cache: use stat() to check if entry is a directoryTimothy Arceri2017-02-101-9/+24
* st/nine: update configure options in the READMEEmil Velikov2017-02-101-2/+1
* loader: unconditionally include unistd.h and stdlib.hNicolai Hähnle2017-02-101-2/+2
* intel/blorp: do not return const data by get_px_size_sa()Emil Velikov2017-02-101-1/+1
* gallium/radeon: use staging for texture read mappings from GTT WCMarek Olšák2017-02-101-4/+5
* gallium/radeon: ignore the level parameter in buffer_transfer_mapMarek Olšák2017-02-101-5/+4
* gallium/radeon: fix performance of buffer readbacksMarek Olšák2017-02-101-8/+9
* radeonsi: align vertex buffer descriptor list size for optimal prefetchMarek Olšák2017-02-104-2/+7
* radeonsi: align shader binaries to CP DMA alignment for optimal prefetchMarek Olšák2017-02-101-1/+2
* radeonsi: move CP_DMA_ALIGNMENT definitionMarek Olšák2017-02-102-10/+10
* radeonsi: remove SI_CONTEXT_FLUSH_AND_INV_FRAMEBUFFERMarek Olšák2017-02-103-6/+6
* radeonsi: remove separate CB/DB_META flush flagsMarek Olšák2017-02-103-17/+8
* radeonsi: reduce the number of FMASK input coordinatesMarek Olšák2017-02-101-7/+3
* radeonsi: write shader asm annotated with wave info into GPU hang reportsMarek Olšák2017-02-103-3/+252
* radeonsi: write wave information into GPU hang reportsMarek Olšák2017-02-101-0/+20
* tgsi-dump: dump label if instruction has oneMarc-André Lureau2017-02-101-11/+13
* tgsi: remove ureg_label_insnMarc-André Lureau2017-02-102-38/+0
* radv: handle queue submission with no cs but semaphoresDave Airlie2017-02-091-2/+20
* util/disk_cache: error check asprintf()Timothy Arceri2017-02-101-5/+7
* nvc0/ir: fix ubo max clamp, reset file indexIlia Mirkin2017-02-091-1/+3
* nv50/ir: always return 0 when trying to read thread id along unit dimIlia Mirkin2017-02-094-5/+17
* nvc0/ir: fix robustness guarantees for constbuf loads on kepler+ computeIlia Mirkin2017-02-091-25/+22
* nvc0: increase number of ubo binding pointsIlia Mirkin2017-02-091-3/+2
* nvc0: expose int64Ilia Mirkin2017-02-091-1/+1
* nvc0/ir: make it possible to have the flags def in def0Ilia Mirkin2017-02-095-12/+15
* nvc0/ir: add support for 64-bit shift lowering on SM20/SM30Ilia Mirkin2017-02-091-6/+62
* nvc0/ir: add support for all the new int64 tgsi opcodesIlia Mirkin2017-02-096-5/+302
* nv50/ir: Split 64-bit integer MAD/MUL operationsPierre Moreau2017-02-091-0/+116
* nvc0/ir: add a "high" subop for shifts, emit shf.l/shf.r for 64-bitIlia Mirkin2017-02-093-3/+74
* nvc0/ir: fix SET and SLCT emissionIlia Mirkin2017-02-092-0/+6
* nvc0/ir: add support for emitting partial min/max ops for int64Ilia Mirkin2017-02-094-1/+14
* gallium: add separate PIPE_CAP_INT64_DIVMODIlia Mirkin2017-02-0918-0/+21
* glsl: Allow compatibility shaders with MESA_GL_VERSION_OVERRIDE=...Matt Turner2017-02-094-4/+14
* i965/fs: add support for int64 to bool conversionSamuel Iglesias Gonsálvez2017-02-091-2/+13
* nir: add opcode to perform int64 to bool conversionsSamuel Iglesias Gonsálvez2017-02-092-0/+2
* i965/fs: Add support for nir_op_[iu]2[iu]32Samuel Iglesias Gonsálvez2017-02-091-0/+4
* i965/fs: Add support for nir_op_[iu]642fSamuel Iglesias Gonsálvez2017-02-091-0/+2
* i965/fs: legalize [u]int64 to 32-bit data conversions in lower_d2xSamuel Iglesias Gonsálvez2017-02-091-1/+3
* i965/fs: Add support for nir_op_[iu]642dJason Ekstrand2017-02-091-0/+2
* i965: Allow int64 conversion operations in channel_expressionsJason Ekstrand2017-02-091-24/+24
* util/disk_cache: stop using ralloc_asprintf() unnecessarilyTimothy Arceri2017-02-091-13/+12
* glsl: add param to force shader recompileTimothy Arceri2017-02-094-4/+5
* util: add a disk_cache_remove() functionTimothy Arceri2017-02-092-0/+34
* st/mesa/i965: create link status enumTimothy Arceri2017-02-0913-21/+32
* radv: Add CPU color packing for VK_FORMAT_A2B10G10R10_UNORM_PACK32.Bas Nieuwenhuizen2017-02-081-2/+6
* mesa: (trivial) include <inttypes.h> for PRIx64 macrosRoland Scheidegger2017-02-081-0/+1
* swr: [rasterizer jitter] Pass LLVM-IR size into jitterTim Rowley2017-02-083-3/+4
* swr: [rasterizer core] Frontend SIMD16 WIPTim Rowley2017-02-084-293/+331
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-19 12:23:50 +0000