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* radeonsi: switch radeon_add_to_buffer_list parameter to si_contextMarek Olšák2018-04-0514-45/+45
| | | | Acked-by: Timothy Arceri <[email protected]>
* radeonsi: use r600_common_context less pt5Marek Olšák2018-04-058-242/+237
| | | | Acked-by: Timothy Arceri <[email protected]>
* radeonsi: use r600_common_context less pt4Marek Olšák2018-04-059-136/+136
| | | | Acked-by: Timothy Arceri <[email protected]>
* radeonsi: use r600_common_context less pt3Marek Olšák2018-04-055-54/+54
| | | | Acked-by: Timothy Arceri <[email protected]>
* radeonsi: use r600_common_context less pt2Marek Olšák2018-04-0510-46/+49
| | | | Acked-by: Timothy Arceri <[email protected]>
* radeonsi: use r600_common_context less pt1Marek Olšák2018-04-059-87/+88
| | | | Acked-by: Timothy Arceri <[email protected]>
* radeonsi: don't use r600_common_context in si_emit_cache_flushMarek Olšák2018-04-051-54/+54
| | | | Acked-by: Timothy Arceri <[email protected]>
* radeonsi: switch r600_atom::emit parameter to si_contextMarek Olšák2018-04-057-24/+19
| | | | Acked-by: Timothy Arceri <[email protected]>
* radeonsi: flatten / remove struct r600_ringMarek Olšák2018-04-0524-179/+175
| | | | Acked-by: Timothy Arceri <[email protected]>
* radeonsi: remove r600_ring::flush callbackMarek Olšák2018-04-054-7/+3
| | | | Acked-by: Timothy Arceri <[email protected]>
* radeonsi: make radeon_add_to_buffer_list_check_mem be gfx-onlyMarek Olšák2018-04-053-39/+36
| | | | Acked-by: Timothy Arceri <[email protected]>
* radeonsi: add_to_buffer_list functions can return voidMarek Olšák2018-04-051-9/+9
| | | | Acked-by: Timothy Arceri <[email protected]>
* radeonsi: move saved_cs functions from r600_pipe_common.c to si_debug.cMarek Olšák2018-04-054-54/+54
| | | | Acked-by: Timothy Arceri <[email protected]>
* radeonsi: move DMA CS functions from r600_pipe_common.c to si_dma_cs.cMarek Olšák2018-04-055-130/+157
| | | | Acked-by: Timothy Arceri <[email protected]>
* radeonsi: move EOP event code from r600_pipe_common.c to si_fence.cMarek Olšák2018-04-054-129/+129
| | | | Acked-by: Timothy Arceri <[email protected]>
* radeonsi: rename si_hw_context.c -> si_gfx_cs.cMarek Olšák2018-04-053-2/+2
| | | | Acked-by: Timothy Arceri <[email protected]>
* radeonsi: move si_destroy_saved_cs to si_debug.cMarek Olšák2018-04-053-8/+8
| | | | Acked-by: Timothy Arceri <[email protected]>
* radeonsi: rename si_begin_new_cs -> si_begin_new_gfx_csMarek Olšák2018-04-053-6/+6
| | | | Acked-by: Timothy Arceri <[email protected]>
* radeonsi: rename si_need_cs_space -> si_need_gfx_cs_spaceMarek Olšák2018-04-056-8/+8
| | | | Acked-by: Timothy Arceri <[email protected]>
* radeonsi: remove r600_pipe_common::blit_decompress_depthMarek Olšák2018-04-054-20/+18
| | | | Acked-by: Timothy Arceri <[email protected]>
* radeonsi: remove r600_pipe_common::decompress_dccMarek Olšák2018-04-056-11/+7
| | | | Acked-by: Timothy Arceri <[email protected]>
* radeonsi: remove r600_pipe_common::invalidate_bufferMarek Olšák2018-04-053-25/+11
| | | | Acked-by: Timothy Arceri <[email protected]>
* radeonsi: remove r600_pipe_common::rebind_bufferMarek Olšák2018-04-054-12/+8
| | | | Acked-by: Timothy Arceri <[email protected]>
* radeonsi: remove r600_common_context::set_occlusion_query_stateMarek Olšák2018-04-054-11/+5
| | | | | | and remove unused old_enable parameter. Acked-by: Timothy Arceri <[email protected]>
* radeonsi: remove r600_pipe_common::save_qbo_stateMarek Olšák2018-04-055-6/+4
| | | | Acked-by: Timothy Arceri <[email protected]>
* radeonsi: remove unused query codeMarek Olšák2018-04-054-77/+2
| | | | | | The get_size perf counter callback is also inlined and removed. Acked-by: Timothy Arceri <[email protected]>
* radeonsi: use num_cs_dw_queries_suspendMarek Olšák2018-04-051-2/+6
| | | | Acked-by: Timothy Arceri <[email protected]>
* radeonsi: remove r600_pipe_common::need_gfx_cs_spaceMarek Olšák2018-04-053-17/+4
| | | | Acked-by: Timothy Arceri <[email protected]>
* radeonsi: remove r600_pipe_common::set_atom_dirtyMarek Olšák2018-04-053-5/+1
| | | | Acked-by: Timothy Arceri <[email protected]>
* radeonsi: remove r600_pipe_common::check_vm_faultsMarek Olšák2018-04-053-9/+2
| | | | Acked-by: Timothy Arceri <[email protected]>
* radeonsi: call CS flush functions directly whenever possibleMarek Olšák2018-04-058-24/+24
| | | | Acked-by: Timothy Arceri <[email protected]>
* radeonsi: skip DCC render feedback checking if color writes are disabledMarek Olšák2018-04-053-5/+23
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* meson: Set .so version for xa like autotools doesDylan Baker2018-04-051-1/+3
| | | | | | | | Fixes: 0ba909f0f111824223bc38563d1a6bc73e69c2cc ("meson: build gallium xa state tracker") Signed-off-by: Dylan Baker <[email protected]> Reviewed-by: Eric Engestrom <[email protected]> Reviewed-by: Emil Velikov <[email protected]>
* anv: Make blorp update the clear color.Rafael Antognolli2018-04-053-63/+66
| | | | | | | | | | | Instead of updating the clear color in anv before a resolve, just let blorp handle that for us during fast clears. v5: Update comment about HiZ clear color (Jordan). Signed-off-by: Rafael Antognolli <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* anv: Use clear address for HiZ fast clears too.Rafael Antognolli2018-04-053-3/+27
| | | | | | | | | Store the default clear address for HiZ fast clears on a global bo, and point to it when needed. Signed-off-by: Rafael Antognolli <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* anv: Emit the fast clear color address, instead of value.Rafael Antognolli2018-04-053-4/+70
| | | | | | | | | | | | | | | On Gen10+, instead of copying the clear color from the state buffer to the surface state, just use the address of the state buffer in the surface state directly. This way we can avoid the copy from state buffer to surface state. v4: - Remove use_clear_address from anv code. (Jason) - Use the helper to extract clear color from attachment (Jason) Signed-off-by: Rafael Antognolli <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* anv: Add a helper to extract clear color from the attachment.Rafael Antognolli2018-04-052-13/+21
| | | | | | | | | Extract the code from color_attachment_compute_aux_usage, so we can later reuse it to update the clear color state buffer. Signed-off-by: Rafael Antognolli <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* i965/surface_state: Emit the clear color address instead of value.Rafael Antognolli2018-04-051-0/+22
| | | | | | | | | | | | On Gen10, when emitting the surface state, use the value stored in the clear color entry buffer by using a clear color address in the surface state. v4: Use the clear color offset from the clear_color_bo, when available. Signed-off-by: Rafael Antognolli <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* i965/blorp: Update the fast clear value buffer.Rafael Antognolli2018-04-052-0/+29
| | | | | | | | | | | | | | | | | | | | | | | | | On Gen10, whenever we do a fast clear, blorp will update the clear color state buffer for us, as long as we set the clear color address correctly. However, on a hiz clear, if the surface is already on the fast clear state we skip the actual fast clear operation and, before gen10, only updated the miptree. On gen10+ we need to update the clear value state buffer too, since blorp will not be doing a fast clear and updating it for us. v4: - do not use clear_value_size in the for loop - Get the address of the clear color from the aux buffer or the clear_color_bo, depending on which one is available. - let core blorp update the clear color, but also update it when we skip a fast clear depth. v5: Better subject (Jordan). v6: Remove outdated comment (Jason). Signed-off-by: Rafael Antognolli <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* i965: Add aux_buf variable to simplify code.Rafael Antognolli2018-04-052-21/+14
| | | | | | | | | | | | In a follow up patch, we make use of clear_color_bo, which is in mt->mcs_buf or mt->hiz_buf. To avoid duplicating more code that does the same thing on both aux buffers, just use aux_buf already. v5: Add aux_buf to brw_wm_surface_state too. v6: Drop aux_surf and use aux_buf->surf instead (Jason). Signed-off-by: Rafael Antognolli <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* i965/miptree: Add new clear color BO for winsys aux buffersRafael Antognolli2018-04-051-0/+17
| | | | | | | | | | | | | Add an extra BO to store clear color when we receive the aux buffer from the window system. Since we have no control over the aux buffer size in this case, we need the new BO to store only the clear color. v5: - Better subject (Jordan). - Drop alignment from brw_bo_alloc(). Signed-off-by: Rafael Antognolli <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* i965/miptree: Add space to store the clear value in the aux surface.Rafael Antognolli2018-04-052-0/+33
| | | | | | | | | | | | | | | | Similarly to vulkan where we store the clear value in the aux surface, we can do the same in GL. v2: Remove unneeded extra function. v3: Use clear_value_state_size instead of clear_value_size. v4: - rename to clear_color_state_size - store clear_color_bo and clear_color_offset in the aux buf struct v5: Unreference clear color bo (Jordan) Signed-off-by: Rafael Antognolli <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* intel/blorp: Update clear color state buffer during fast clears.Rafael Antognolli2018-04-051-0/+48
| | | | | | | | | | | | | | | | | | We always want to update the fast clear color during a fast clear on i965. On anv, we are doing that before a resolve, but by adding support to blorp, we can do a similar thing and update it during a fast clear instead. The goal is to remove some code from anv that does such update, and centralize everything in blorp, hopefully removing a lot of code duplication. It also allows us to have a similar behavior on gen < 9 and gen >= 10. v5: s/we/we are/ (Jordan) Signed-off-by: Rafael Antognolli <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* intel/blorp: Only copy clear color when doing a resolve.Rafael Antognolli2018-04-051-4/+9
| | | | | | | | | We only need to copy the clear color from the state buffer to the inlined surface state when doing a resolve. Signed-off-by: Rafael Antognolli <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* intel/blorp: Add support for fast clear address.Rafael Antognolli2018-04-051-5/+13
| | | | | | | | | | | | On gen10+, if surface->clear_color_addr is present, use it directly intead of copying it to the surface state. v4: Remove redundant #if clause for GEN <= 10 (Jason) v5: Move flush after the reloc, and keep lower bits (Topi). Signed-off-by: Rafael Antognolli <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* intel/isl: Add support to emit clear value address.Rafael Antognolli2018-04-052-4/+23
| | | | | | | | | | | | | | gen10 can emit the clear color by setting it on a buffer somewhere, and then adding only the address to the surface state. This commit add support for that on isl_surf_fill_state, and if that is requested, skip setting the clear value itself. v2: Add assert to make sure we are at least on gen10. Signed-off-by: Rafael Antognolli <[email protected]> Reviewed-by: Jordan Justen <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* intel: Use Clear Color struct size.Rafael Antognolli2018-04-056-15/+35
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | The size of the clear color struct (expected by the hardware) is 8 dwords (isl_dev.ss.clear_value_state_size here). But we still need to track the size of the clear color, used when memcopying it to/from the state buffer. For that we keep isl_dev.ss.clear_value_size. v4: - Add struct to gen11 too (Jason, Jordan) - Add field for Converted Clear Color to gen11 (Jason) - Add clear_color_state_offset to differentiate from clear_value_offset. - Fix all the places where clear_value_size was used. v5 (Jason): - Split genxml changes to another commit. - Remove unnecessary gen checks. - Bring back missing offset increment to init_fast_clear_color(). v6 (Jason): - On init_fast_clear_color, change: addr.offset += 4 => sdi.Address.offset += i * 4 - Use GEN_GEN instead of GEN_VERSIONx10. [[email protected]: isl_device_init changes] Signed-off-by: Rafael Antognolli <[email protected]> Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* intel/genxml: Add Clear Color struct to gen10+.Rafael Antognolli2018-04-052-0/+18
| | | | | | | v5: Split genxml changes into its own commit (Jason). Signed-off-by: Rafael Antognolli <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* intel/genxml: Use a single field for clear color address on gen10.Rafael Antognolli2018-04-052-8/+6
| | | | | | | | | | | | | | | | | | | | genxml does not support having two address fields with different names but same position in the state struct. Both "Clear Color Address" and "Clear Depth Address Low" mean the same thing, only for different surface types. To workaround this genxml limitation, rename "Clear Color Address" to "Clear Value Address" and use it for both color and depth. Do the same for the high bits. TODO: add support for multiple addresses at the same position in the xml. v2: Combine high and low order bits into a single address field. Signed-off-by: Rafael Antognolli <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* genxml: Preserve fields that share dword space with addresses.Rafael Antognolli2018-04-051-2/+6
| | | | | | | | | | | | | | | | | Some instructions contain fields that are either an address or a value of some type based on the content of other fields, such as clear color values vs address. That works fine if these fields are in the less significant dword, the lower 32 bits of the address, because they get OR'ed with the address. But if they are in the higher 32 bits, they get discarded. On Gen10 we have fields that share space with the higher 16 bits of the address too. This commit makes sure those fields don't get discarded. v5: Remove spurious whitespace (Jason). Signed-off-by: Rafael Antognolli <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
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