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* nir: find induction/limit vars in iand instructionsTimothy Arceri2019-03-121-8/+91
* nir: pass nir_op to calculate_iterations()Timothy Arceri2019-03-121-7/+10
* nir: add get_induction_and_limit_vars() helper to loop analysisTimothy Arceri2019-03-121-15/+26
* nir: add helper to return inversion op of a comparisonTimothy Arceri2019-03-121-0/+29
* nir: simplify the loop analysis trip count code a littleTimothy Arceri2019-03-121-81/+82
* nir: unroll some loops with a variable limitTimothy Arceri2019-03-121-0/+55
* nir: calculate trip count for more loopsTimothy Arceri2019-03-123-6/+49
* nir: add partial loop unrolling supportTimothy Arceri2019-03-121-8/+199
* nir: add new partially_unrolled bool to nir_loopTimothy Arceri2019-03-122-0/+2
* nir: add guess trip count support to loop analysisTimothy Arceri2019-03-122-6/+86
* panfrost: Add support for PAN_MESA_DEBUGTomeu Vizoso2019-03-126-27/+88
* panfrost/midgard: Add support for MIDGARD_MESA_DEBUGTomeu Vizoso2019-03-122-22/+50
* nir/spirv: Fix assert when unsampled OpTypeImage has unknown 'Depth'Xavier Bouchoux2019-03-111-3/+4
* iris: Fix write enable in pinning of depth/stencil resourcesKenneth Graunke2019-03-111-12/+14
* iris: Refactor depth/stencil buffer pinning into a helper.Kenneth Graunke2019-03-111-37/+28
* iris: Move depth/stencil flushes so they actually do somethingKenneth Graunke2019-03-112-4/+5
* st/dri: allow direct UYVY importChristian Gmeiner2019-03-111-0/+2
* iris: Fix TES gl_PatchVerticesIn handling.Kenneth Graunke2019-03-112-3/+11
* iris: Rework default tessellation level uploadsKenneth Graunke2019-03-112-39/+33
* iris: Face should be a system value.Timur Kristóf2019-03-111-0/+1
* vc4: Switch the post-RA scheduler over to the DAG datastructure.Eric Anholt2019-03-111-110/+73
* v3d: Use the DAG datastructure for QPU instruction scheduling.Eric Anholt2019-03-112-117/+75
* vc4: Reuse list_for_each_entry_rev().Eric Anholt2019-03-111-2/+2
* v3d: Reuse list_for_each_entry_rev().Eric Anholt2019-03-111-2/+2
* vc4: Switch over to using the DAG datastructure for QIR scheduling.Eric Anholt2019-03-111-79/+55
* util: Add a DAG datastructure.Eric Anholt2019-03-114-0/+222
* freedreno/a6xx: Remove extra parensKristian H. Kristensen2019-03-111-1/+1
* freedreno: Use c_vis_args and no_override_init_argsKristian H. Kristensen2019-03-111-1/+1
* turnip: preliminary support for Wayland WSIChia-I Wu2019-03-116-1/+358
* turnip: preliminary support for tu_GetImageSubresourceLayoutChia-I Wu2019-03-111-5/+11
* turnip: Use Vulkan 1.1 names instead of KHRChad Versace2019-03-118-100/+100
* turnip: preliminary support for tu_CmdDrawChia-I Wu2019-03-111-0/+83
* turnip: preliminary support for draw state bindingChia-I Wu2019-03-112-4/+357
* turnip: add draw_cs to tu_cmd_bufferChia-I Wu2019-03-112-3/+21
* turnip: parse VkPipelineVertexInputStateCreateInfoChia-I Wu2019-03-112-0/+134
* turnip: parse VkPipelineShaderStageCreateInfoChia-I Wu2019-03-112-0/+602
* turnip: compile VkPipelineShaderStageCreateInfoChia-I Wu2019-03-112-0/+143
* turnip: preliminary support for shader modulesChia-I Wu2019-03-115-5/+411
* turnip: parse VkPipeline{Multisample,ColorBlend}StateCreateInfoChia-I Wu2019-03-113-0/+355
* turnip: parse VkPipelineDepthStencilStateCreateInfoChia-I Wu2019-03-112-2/+204
* turnip: parse VkPipelineRasterizationStateCreateInfoChia-I Wu2019-03-112-0/+128
* turnip: parse VkPipelineViewportStateCreateInfoChia-I Wu2019-03-112-1/+130
* turnip: parse VkPipelineInputAssemblyStateCreateInfoChia-I Wu2019-03-112-0/+49
* turnip: parse VkPipelineDynamicStateCreateInfoChia-I Wu2019-03-111-0/+46
* turnip: create a less dummy pipelineChia-I Wu2019-03-112-30/+109
* turnip: simplify tu_cs sub-streams usageChia-I Wu2019-03-112-7/+12
* turnip: fix tu_cs sub-streamsChia-I Wu2019-03-111-1/+5
* turnip: tu_cs_emit_arrayChia-I Wu2019-03-111-0/+11
* turnip: add tu_cs_discard_entriesChia-I Wu2019-03-111-0/+11
* turnip: more/better asserts for tu_csChia-I Wu2019-03-111-2/+4
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