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* python: Specify the template output encodingMathieu Bridon2018-08-072-2/+2
* python: Fix rich comparisonsMathieu Bridon2018-08-073-12/+13
* python: Use explicit integer divisionsMathieu Bridon2018-08-076-16/+19
* egl/main: Add bits for EGL_KHR_mutable_render_bufferChad Versace2018-08-075-4/+93
* dri: Add param driCreateConfigs(mutable_render_buffer)Chad Versace2018-08-078-13/+19
* dri: Define DRI_MutableRenderBuffer extensionsChad Versace2018-08-074-0/+10
* egl/dri2: In dri2_make_current, return early on failureChad Versace2018-08-071-14/+15
* egl: Simplify queries for EGL_RENDER_BUFFERChad Versace2018-08-075-20/+85
* radeonsi: set GLC=1 for all write-only shader resourcesMarek Olšák2018-08-071-2/+19
* radeonsi: don't load block dimensions into SGPRs if they are not variableMarek Olšák2018-08-073-7/+7
* egl: set EGL_BAD_NATIVE_PIXMAP in the copy_buffers fallbackEmil Velikov2018-08-071-1/+2
* egl/x11: use the no-op dri2_fallback_copy_buffers for swrastEmil Velikov2018-08-071-1/+2
* egl: remove unneeded _eglGetNativePlatform checkEmil Velikov2018-08-071-2/+0
* autoconf: stop exporting internal wayland detailsEmil Velikov2018-08-073-4/+4
* meson: stop exporting internal wayland detailsEmil Velikov2018-08-071-2/+2
* swr: don't export swr_create_screen_internalEmil Velikov2018-08-072-2/+1
* i965: gen_shader_sha1() doesn't use the brw_contextEric Engestrom2018-08-071-4/+4
* intel: don't build tools without -Dtools=intelLionel Landwerlin2018-08-072-15/+15
* virgl: update virgl_hw.h from virglrendererErik Faye-Lund2018-08-071-1/+26
* virgl: rename msaa_sample_positions -> sample_locationsErik Faye-Lund2018-08-072-5/+5
* vc4: Fix a leak of the no-vertex-elements workaround BO.Eric Anholt2018-08-061-0/+2
* vc4: Fix context creation when syncobjs aren't supported.Eric Anholt2018-08-061-2/+6
* v3d: Emit the VCM_CACHE_SIZE packet.Eric Anholt2018-08-066-4/+45
* v3d: Drop "VC5" from the renderer string.Eric Anholt2018-08-061-1/+1
* v3d: Avoid spilling that breaks the r5 usage after a ldvary.Eric Anholt2018-08-061-0/+9
* v3d: Make sure that QPU instruction-has-a-dest matches VIR.Eric Anholt2018-08-062-1/+11
* v3d: Wait for TMU writes to complete before continuing after a spill.Eric Anholt2018-08-061-1/+6
* v3d: Make sure we don't emit a thrsw before the last one finished.Eric Anholt2018-08-061-2/+13
* v3d: Add some debug code for forcing register spilling.Eric Anholt2018-08-061-0/+14
* drisw: Fix build on Android Nougat, which lacks shm (v2)Chad Versace2018-08-061-0/+11
* mesa: fix make check for AMD_framebuffer_multisample_advancedIan Romanick2018-08-061-0/+8
* glapi: Fix GLES versioning for AMD_framebuffer_multisample_advanced functionsIan Romanick2018-08-061-2/+2
* anv: add more swapchain formatsTapani Pälli2018-08-061-5/+11
* nvc0/ir: return 0 in imageLoad on incomplete texturesKarol Herbst2018-08-042-3/+31
* gm200/ir: optimize rcp(sqrt) to rsqKarol Herbst2018-08-041-1/+10
* gm200/ir: add native OP_SQRT supportKarol Herbst2018-08-044-2/+14
* intel: tools: simplify meson buildLionel Landwerlin2018-08-041-46/+50
* intel: aubinator: simplify decodingLionel Landwerlin2018-08-041-10/+5
* intel: common: add missing stdint includeLionel Landwerlin2018-08-041-0/+2
* intel: decoder: remove unused variableLionel Landwerlin2018-08-041-2/+0
* intel: tools: aubwrite: reuse canonical address helperLionel Landwerlin2018-08-041-17/+2
* intel: aubinator: fix read the context/ringLionel Landwerlin2018-08-041-2/+2
* nir: Transform expressions of b2f(a) and b2f(b) to a == bIan Romanick2018-08-041-0/+3
* nir: Transform expressions of b2f(a) and b2f(b) to a ^^ bIan Romanick2018-08-041-0/+3
* nir: Transform expressions of b2f(a) and b2f(b) to !(a && b)Ian Romanick2018-08-041-0/+3
* nir: Transform expressions of b2f(a) and b2f(b) to a && bIan Romanick2018-08-041-0/+3
* nir: Transform expressions of b2f(a) and b2f(b) to !(a || b)Ian Romanick2018-08-041-0/+11
* nir: Transform -fabs(a) >= 0 to a == 0Ian Romanick2018-08-041-0/+9
* nir: Transform expressions of b2f(a) and b2f(b) to a || bIan Romanick2018-08-041-0/+19
* nir: Transform -fabs(a) < 0 to a != 0Ian Romanick2018-08-041-0/+4
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