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* nvc0/ir: safen up lowering logic against overwriting reused valuesIlia Mirkin2018-01-071-2/+4
| | | | | | | | | I'm fairly sure both of the changed sites are OK as-is, but they're fragile, so this is just safening them up. Since this is happening pre-ssa, we don't want to be overwriting values that may potentially get used later on. Signed-off-by: Ilia Mirkin <[email protected]>
* nvc0: update tic in-place when buffer address changesIlia Mirkin2018-01-072-14/+21
| | | | | | This is helpful for bindless, where changing TIC id's is undesirable. Signed-off-by: Ilia Mirkin <[email protected]>
* nvc0: ensure that pushbuf keeps ref to old text/tls bosIlia Mirkin2018-01-071-0/+13
| | | | | | | | | If we free the bo, then the PTE may get deallocated immediately. We have to make sure that the submission includes a ref to the old bo so that it remains mapped for the duration of the command execution. Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]>
* i965: Torch public intel_batchbuffer_emit_dword/float helpers.Kenneth Graunke2018-01-062-15/+2
| | | | | | | | | | | intel_batchbuffer_emit_float is dead code, it should go. intel_batchbuffer_emit_dword only had one user, which had bungled using them by forgetting to call intel_batchbuffer_require_space first. So it seems wise to delete these unsafe helpers. Cc: [email protected] Reviewed-by: Jason Ekstrand <[email protected]>
* i965: Require space for MI_BATCHBUFFER_END.Kenneth Graunke2018-01-061-2/+5
| | | | | | | | | | | intel_batchbuffer_emit_dword doesn't reserve space for the DWord it emits. In the past, we had some reserved batch space to ensure this worked. With the switch to growing batches, we need to actually request space so that we grow if necessary. Fixes: 2c46a67b4138631217141f (i965: Delete BATCH_RESERVED handling.) Cc: [email protected] Reviewed-by: Jason Ekstrand <[email protected]>
* i965: Shut up a few unused variable warnings.Kenneth Graunke2018-01-061-2/+2
| | | | | If asserts are disabled, you get pointless warnings about devinfo being used (it's used to assert on devinfo->gen).
* ac: add ac_build_fmin/fmax helpersMarek Olšák2018-01-062-15/+22
| | | | Reviewed-by: Samuel Pitoiset <[email protected]>
* mesa: remove dd_function_table::GetCompressedTexSubImage and clean it upMarek Olšák2018-01-065-32/+11
| | | | Reviewed-by: Ian Romanick <[email protected]>
* mesa: Tidy up the 4.6 section of GL4x.xmlNeil Roberts2018-01-061-5/+10
| | | | | | | | The enums are moved to the top and indented like the rest of the file. Comments are added to split up the function aliases by corresponding extension. This should make no functional difference. Reviewed-by: Ian Romanick <[email protected]>
* radv: remove unused radv_color_buffer_info::cb_clear_valueXSamuel Pitoiset2018-01-051-2/+0
| | | | | | | Found by inspection. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas nieuwenhuizen <[email protected]>
* anv: Take write mask into account in has_color_buffer_write_enabledAlex Smith2018-01-051-9/+18
| | | | | | | | | | | | | | | | | | | | If we have a color attachment, but its writes are masked, this would have still returned true. This is inconsistent with how HasWriteableRT in 3DSTATE_PS_BLEND is set, which does take the mask into account. This could lead to PixelShaderHasUAV not being set in 3DSTATE_PS_EXTRA if the fragment shader does use UAVs, meaning the fragment shader may not be invoked because HasWriteableRT is false. Specifically, this was seen to occur when the shader also enables early fragment tests: the fragment shader was not invoked despite passing depth/stencil. Fix by taking the color write mask into account in this function. This is consistent with how things are done on i965. Signed-off-by: Alex Smith <[email protected]> Cc: [email protected] Reviewed-by: Iago Toral Quiroga <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]>
* mesa: Add GL4.6 aliases of functions from GL_ARB_indirect_parametersNeil Roberts2018-01-051-0/+22
| | | | Reviewed-by: Ian Romanick <[email protected]>
* radv: enable denorms for 64-bit and 16-bit floatsSamuel Pitoiset2018-01-051-0/+14
| | | | | | | | | | | Similar to RadeonSI. This fixes: dEQP-VK.image.texel_view_compatible.graphic.basic.attachment_read.bc*r16g16b16a16_sfloat dEQP-VK.image.extended_usage_bit.attachment_write.r16_sfloat Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* amd/common: correctly detect if we need ring buffersSamuel Pitoiset2018-01-051-7/+9
| | | | | | | | | | | | When allocate_user_sgprs() was called, ctx->stage was actually unset and 0 is for the vertex shader. This doesn't change anything for now because of the spill support thing. Though, the number of user SGPRs has to be fixed for merged shaders on GFX9. It was broken before anyway. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* amd/common: use ac_image_load when lod is zeroSamuel Pitoiset2018-01-051-1/+3
| | | | | | | | | This might decrease VGPR spilling, because we no longer have to use v4i32 for 2D fetches when level == 0. We now use v2i32 for those cases. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* radv: limit the scissor bug workaround to Vega 10 and RavenSamuel Pitoiset2018-01-051-1/+6
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* glsl/standalone: set MaxTransformFeedbackBuffersAlejandro Piñeiro2018-01-051-0/+3
| | | | | | | | Using 4, as it is the default value on mesa. See mesa/main/config.h and the following commit that introduced the value: 15ac66e331abdab12e882d80a6b4f647bc905298 Reviewed-by: Ian Romanick <[email protected]>
* glsl/standalone: set MaxVertexStreamsAlejandro Piñeiro2018-01-051-0/+3
| | | | | | | ARB_transform_feedback3 sets a minimum of 1, ARB_gpu_shader5 a minimum of 4. It shouldn't matter too much, so choosing the later. Reviewed-by: Ian Romanick <[email protected]>
* glsl/standalone: set MaxUniformBufferBindingsAlejandro Piñeiro2018-01-051-0/+3
| | | | | | | | Used to handle how many ubo you can define on the context. Minimimum defined as 36 on ARB_uniform_buffer_object spec, up to 84 on OpenGL 4.6 (12 per stage at each moment). Reviewed-by: Ian Romanick <[email protected]>
* glsl/standalone: point which arguments are mandatoryAlejandro Piñeiro2018-01-051-1/+4
| | | | | | | Every now and then I execute the standalone compiler, get the non-version error, and need to remember what I'm doing wrong Reviewed-by: Ian Romanick <[email protected]>
* ac: rework ac_llvm_extract_elem()Timothy Arceri2018-01-051-3/+3
| | | | | | | Simplifies the logic a little and asserts index is 0. Suggested-by: Nicolai Hähnle <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* st/glsl_to_nir/radeonsi: enable tessellation shadersTimothy Arceri2018-01-052-1/+5
| | | | | Reviewed-by: Nicolai Hähnle <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* gallium/tgsi: add patch support to tgsi_get_gl_varying_semantic()Timothy Arceri2018-01-051-3/+8
| | | | | Reviewed-by: Nicolai Hähnle <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: add dummy implementation of si_nir_scan_tess_ctrl()Timothy Arceri2018-01-053-0/+23
| | | | | Reviewed-by: Nicolai Hähnle <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* ac/radeonsi: add load_tess_coord() to the abiTimothy Arceri2018-01-053-24/+42
| | | | | Reviewed-by: Nicolai Hähnle <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: make si_llvm_emit_tcs_epilogue compatible with emit_outputs abiTimothy Arceri2018-01-051-3/+7
| | | | | Reviewed-by: Nicolai Hähnle <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* radeonsi/nir: gather tess propertiesTimothy Arceri2018-01-051-0/+29
| | | | | Reviewed-by: Nicolai Hähnle <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* ac/radeonsi: add tcs_rel_ids to the abiTimothy Arceri2018-01-054-18/+18
| | | | | Reviewed-by: Nicolai Hähnle <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: add unpack_llvm_param() helperTimothy Arceri2018-01-051-6/+12
| | | | | | | | This allows us to pass the llvm param directly rather than looking it up. Reviewed-by: Nicolai Hähnle <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* ac: add {tcs,tes}_patch_id to the abiTimothy Arceri2018-01-054-19/+16
| | | | | Reviewed-by: Nicolai Hähnle <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: add nir support for tcs outputsTimothy Arceri2018-01-051-0/+118
| | | | | Reviewed-by: Nicolai Hähnle <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* ac: move some helpers to ac_llvm_build.cTimothy Arceri2018-01-053-40/+50
| | | | | | | We will call these from the radeonsi NIR backend. Reviewed-by: Nicolai Hähnle <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* ac: add store_tcs_outputs() to the abiTimothy Arceri2018-01-052-24/+51
| | | | | Reviewed-by: Nicolai Hähnle <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: add si_nir_load_input_tcs()Timothy Arceri2018-01-051-0/+45
| | | | | | V2: drop type param and just use ctx->i32 Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: add get_dw_address_from_generic_indices() helperTimothy Arceri2018-01-051-30/+46
| | | | | | | This will be used by both the tgsi and nir backends. Reviewed-by: Nicolai Hähnle <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* ac: call load_tcs_input() via the abiTimothy Arceri2018-01-051-19/+17
| | | | | | | | This also enables some code sharing with tes. V2: drop type param and just use ctx->i32 Reviewed-by: Marek Olšák <[email protected]>
* ac: add load_tes_inputs() to the abiTimothy Arceri2018-01-053-22/+52
| | | | | | V2: drop type param and just use ctx->i32 Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: add si_nir_load_input_tes()Timothy Arceri2018-01-052-0/+59
| | | | | | V2: drop type param and just use ctx->i32 Reviewed-by: Marek Olšák <[email protected]>
* swr/rast: fix invalid sign masks in avx512 simdlib codeTim Rowley2018-01-043-3/+3
| | | | | | | Should be 0x80000000 instead of 0x8000000. Cc: [email protected] Reviewed-by: Bruce Cherniak <[email protected]>
* radv: Use correct flush bits for flushing L2 during CB/DB flushes.Bas Nieuwenhuizen2018-01-041-13/+16
| | | | | | | | | | | | Copied from radeonsi. Putting in the correct metadata flush commands for eventually not flushing L2 on CB/DB switch. Does not remove the need for V_028A90_CACHE_FLUSH_AND_INV_TS_EVENT at the moment. Reviewed-by: Samuel Pitoiset <[email protected]>
* radv: Invalidate L1 for VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT.Bas Nieuwenhuizen2018-01-041-1/+1
| | | | | | | These are just shaders reads, so we need to invalidate L1. Fixes: 6dbb0eaccc "radv: handle subpass cache flushes" Reviewed-by: Samuel Pitoiset <[email protected]>
* radv/gfx9: reduce the number of input VGPRs for the GS stageSamuel Pitoiset2018-01-041-1/+14
| | | | | | | This can still be improved, but let's start with this. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* amd/common: scan if gl_PrimitiveID is used before translating to LLVMSamuel Pitoiset2018-01-045-10/+7
| | | | | | | | | It makes more sense to move all scan stuff in the same place. Also, we don't really need to duplicate the uses_primid field for each stages. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* amd/common: scan if gl_InvocationID is usedSamuel Pitoiset2018-01-042-0/+4
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* egl/android: Fix build break with dri2_initialize_android _EGLDisplay parameterRob Herring2018-01-041-15/+15
| | | | | | | | | | | | | | | | Commit 2f421651aca9 ("egl: let each platform decided how to handle LIBGL_ALWAYS_SOFTWARE") broke the build due to copy-n-paste of misnamed function parameter.: src/egl/drivers/dri2/platform_android.c:1183:8: error: use of undeclared identifier 'disp' Rather than just fixing 'disp', rename the function parameter 'dpy' to 'disp' to align with the other EGL platforms' implementations. Fixes: 2f421651aca9 ("egl: let each platform decided how to handle LIBGL_ALWAYS_SOFTWARE") Reviewed-by: Tapani Pälli <[email protected]> Acked-by: Eric Engestrom <[email protected]> Signed-off-by: Rob Herring <[email protected]>
* anv: Add missing unlock in anv_scratch_pool_allocAlex Smith2018-01-041-1/+3
| | | | | | | | | Fixes hangs seen due to the lock not being released here. Signed-off-by: Alex Smith <[email protected]> Cc: [email protected] Reviewed-by: Lionel Landwerlin <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* mesa/bindless: fix missing image _Layer initializationIlia Mirkin2018-01-041-0/+1
| | | | | | | | | | | Some later code relies on _Layer to set first/last_layer. Make sure it's always initialized. Detected by valgrind's conditional jump/move with uninit value logic. Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]>
* radeonsi: fix alpha-to-coverage if color writes are disabledJózef Kucia2018-01-041-0/+3
| | | | | | | | If alpha-to-coverage is enabled, we have to compute alpha even if color writes are disabled. Signed-off-by: Józef Kucia <[email protected]> Signed-off-by: Marek Olšák <[email protected]>
* ac: rename has_sync_file to has_fence_to_handle.Bas Nieuwenhuizen2018-01-044-6/+6
| | | | | | | | | | | sync_files are in linux since 4.7, while the amdgpu fence_to_handle ioctl is only in 4.15. In particular we don't need it for sync_file in radv, because everything happens via syncobjs, which got support earlier than fence_to_handle. Reviewed-by: Marek Olšák <[email protected]>
* ac/nir: Handle loading data from compact arrays.Bas Nieuwenhuizen2018-01-041-6/+7
| | | | | Fixes: f4e499ec791 "radv: add initial non-conformant radv vulkan driver" Reviewed-by: Dave Airlie <[email protected]>
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