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* loader/dri3: Try to make sure we only process our own NotifyMSC eventsMichel Dänzer2018-01-172-22/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | We were using a sequence counter value to wait for a specific NotifyMSC event. However, we can receive events from other clients as well, which may already be using higher sequence numbers than us. In that case, we could stop processing after an event from another client, which could have been received significantly earlier. This would have multiple undesirable effects: * The computed MSC and UST values would be lower than they should be * We could leave a growing number of NotifyMSC events from ourselves and other clients in XCB's special event queue I ran into this with Firefox and Thunderbird, whose VSync threads both seem to use the same window. The result was sluggish screen updates and growing memory consumption in one of them. Fix this by checking the XCB sequence number and MSC value of NotifyMSC events, instead of using our own sequence number. v2: * Use the Present event ID for the sequence parameter of the PresentNotifyMSC request, as another safeguard against processing events from other clients * Rebase on drawable mutex changes Reviewed-by: Nicolai Hähnle <[email protected]> # v1
* radv: Implement VK_EXT_debug_report.Bas Nieuwenhuizen2018-01-173-0/+50
| | | | | | | | This is not hooked up to any messages yet, but useful for e.g. renderdoc if you add some messages during development. Reviewed-by: Dave Airlie <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]>
* vulkan: move anv VK_EXT_debug_report implementation to common code.Bas Nieuwenhuizen2018-01-179-95/+182
| | | | | | | | | | For also using it in radv. I moved the remaining stubs back to anv_device.c as they were just trivial. This does not move the vk_errorf/anv_perf_warn or the object type macros, as those depend on anv types and logging. Reviewed-by: Tapani Pälli <[email protected]>
* st/glsl_to_nir: disable io lowering to temps for tessTimothy Arceri2018-01-171-4/+8
| | | | | | | | | | | | | | Lowering these to temps makes a big mess, and results in some piglit test failures. Also the radeonsi backend (the only backend to support tess) has support for indirects so there is no need to lower them anyway. Fixes the following piglit tests on radeonsi: tests/spec/arb_tessellation_shader/execution/variable-indexing/tes-input-array-vec3-index-rd.shader_test tests/spec/arb_tessellation_shader/execution/variable-indexing/tes-input-array-vec4-index-rd.shader_test Reviewed-by: Marek Olšák <[email protected]>
* i965: Enable CCS_E sampling of sRGB textures as UNORMJason Ekstrand2018-01-161-3/+2
| | | | | Reviewed-by: Iago Toral Quiroga <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/draw: Do resolves properly for textures used by TXFJason Ekstrand2018-01-161-0/+41
| | | | | Reviewed-by: Iago Toral Quiroga <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/miptree: Refactor CCS_E and CCS_D cases in render_aux_usageJason Ekstrand2018-01-161-13/+15
| | | | | | | | | | | | | | | | | | | | | This commit unifies the CCS_E and CCS_D cases. This should fix a couple of subtle issues. One is that when you use INTEL_DEBUG=norbc to disable CCS_E, we don't get the sRGB blending workaround. By unifying the code, we give CCS_D that workaround as well. The second issue fixed by this refactor is that the blending workaround was appears to be enabled on all gens but really only applies on gen9. Due to a happy accident in the way code was laid out, it was only getting enabled on gen9: gen8 and earlier don't support non-zero-one clear colors, and gen10 supports sRGB for CCS_E so it got caught in the format_ccs_e_compat_with_miptree case. This refactor moves it above the format_ccs_e_compat_with_miptree case so it's an explicit early exit and makes it explicitly only on gen9. Reviewed-by: Nanley Chery <[email protected]> Reviewed-by: Iago Toral Quiroga <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Cc: "17.3" <[email protected]>
* Re-enable regular fast-clears (CCS_D) on gen9+Jason Ekstrand2018-01-162-42/+25
| | | | | | | | | | | | | This reverts commit ee57b15ec764736e2d5360beaef9fb2045ed0f68, "i965: Disable regular fast-clears (CCS_D) on gen9+". How taht we've fixed the issue with too many different aux usages in the render cache, it should be safe to re-enable CCS_D for sRGB. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104163 Tested-by: Eero Tamminen <[email protected]> Reviewed-by: Iago Toral Quiroga <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Cc: "17.3" <[email protected]>
* i965: Track format and aux usage in the render cacheJason Ekstrand2018-01-165-27/+92
| | | | | | | | | | | | | | | | This lets us perform render cache flushes whenever a surface goes from being used with one aux+format to a different aux+format. This is the "proper" fix for https://bugs.freedesktop.org/102435. ee57b15ec764736e2d5360beaef9fb2045ed0f68 which was really just a partial revert of 3e57e9494c2279580ad6a83ab8c065d01e7e634e was just a hack to get rid of a hang in a bunch of Valve games. This solves the actual problem responsible for the hang and lets us enable CCS_E once again. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102435 Reviewed-by: Iago Toral Quiroga <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Cc: "17.3" <[email protected]>
* i965: Call brw_cache_flush_for_render in predraw_resolve_framebufferJason Ekstrand2018-01-161-0/+2
| | | | | | | | | | | | | This makes sure we flush things out of other caches prior to using a surface through the render cache. Currently, this is a no-op because GL won't let you bind anything other than a color surface as color so it should never end up in the depth cache. However, this does complete the flush/add_bo pair for regular drawing which will be required for the next commit. Reviewed-by: Iago Toral Quiroga <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Cc: "17.3" <[email protected]>
* i965/gen6-7/sol: Bump primitive counter BO size.Francisco Jerez2018-01-161-2/+3
| | | | | | | | | | Improves performance of SynMark2 OglGSCloth by a further 9.65%±0.59% due to the reduction in overwraps of the primitive count buffer that lead to a CPU stall on previous rendering. Cummulative performance improvement from the series 81.50% ±0.96% (data gathered on VLV). Tested-By: Eero Tamminen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/gen6-7/sol: Keep independent counters for the current and previous ↵Francisco Jerez2018-01-163-27/+36
| | | | | | | | | | | | | | | | | | begin/end block. This allows us to aggregate the primitive counts of a completed transform feedback begin/end block lazily, which in the most typical case (where glDrawTransformFeedback is not used) will allow us to avoid aggregating the primitive counters on the CPU altogether, preventing a stall on previous rendering during glBeginTransformFeedback(), which dramatically improves performance of applications that rely heavily on transform feedback. Improves performance of SynMark2 OglGSCloth by 65.52% ±0.25% (data gathered on VLV). Tested-By: Eero Tamminen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/gen6-7/sol: Restructure primitive counter into a separate type.Francisco Jerez2018-01-163-39/+58
| | | | | | | | | | | A primitive counter encapsulates a scalar aggregating counter for each vertex stream along with a section within the primitive tally buffer which hasn't been read out yet. Defining this as a separate type will allow us to keep multiple counter objects around for the same transform feedback object without any code duplication. Tested-By: Eero Tamminen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* st/mesa: enable ARB_enhanced_layouts on nir driversTimothy Arceri2018-01-171-3/+1
| | | | | | | | | I'm guessing this may have been disable because of missing component packing support. However recent nir linking changes required nir based gallium drivers to support component packing so this should now be ok to enable. Reviewed-by: Marek Olšák <[email protected]>
* draw: remove VSPLIT_CREATE_IDX macroRoland Scheidegger2018-01-171-11/+12
| | | | | | | Just inline the little bit of code. Reviewed-by: Jose Fonseca <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* draw: fix vsplit code when the (post-bias) index value is -1Roland Scheidegger2018-01-172-3/+4
| | | | | | | | | | | | | | | | | | | vsplit_add_cache uses the post-bias index for hashing, but the vsplit_add_cache_uint/ushort/ubyte ones used the pre-bias index, therefore the code for handling the special case (because -1 matches the initialization value of the cache) wasn't actually working. Commit 78a997f72841310620d18daa9015633343d04db1 actually simplified the cache logic somewhat, but it looks like this particular problem carried over (and duplicated to the ushort/ubyte cases, since before only uint needed it). This could lead to the vsplit cache doing the wrong thing, in particular later fetch_info might indicate there are 0 values to fetch. This only really affected edge cases which were bogus to begin with, but it could lead to a crash with the jit vertex shader, since it cannot handle this case correctly (the count loop is always executed at least once and we would not allocate any memory for the shader outputs), so add another assert to catch it there. Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Jose Fonseca <[email protected]>
* st/va: release held locks in error pathsGrazvydas Ignotas2018-01-173-3/+9
| | | | | | | | | | | | | | | | | | | | | | | | Found with the help of following Coccinelle semantic patch: // <smpl> @@ expression E; @@ \(pthread_mutex_lock\|mtx_lock\|simple_mtx_lock\)(E) ... ( \(pthread_mutex_unlock\|mtx_unlock\|simple_mtx_unlock\)(E); ... return ...; | + maybe need_unlock(E); return ...; ) // </smpl> Signed-off-by: Grazvydas Ignotas <[email protected]> Reviewed-by: Christian König <[email protected]> Cc: [email protected]
* mesa: remove unneeded semicolonsGrazvydas Ignotas2018-01-173-3/+3
| | | | | | Trivial. Found by Coccinelle. Reviewed-by: Eric Engestrom <[email protected]>
* radeon: remove unneeded semicolonsGrazvydas Ignotas2018-01-174-6/+6
| | | | | | Trivial. Found by Coccinelle. Reviewed-by: Eric Engestrom <[email protected]>
* osmesa: don't check SmoothFlag twiceGrazvydas Ignotas2018-01-171-1/+0
| | | | | | Trivial. Found by Coccinelle. Reviewed-by: Eric Engestrom <[email protected]>
* ac: set no-signed-zeros-fp-math when RADV_DEBUG="unsafemath" is usedSamuel Pitoiset2018-01-161-0/+3
| | | | | | | | | | | This is an optimisation that is recommended by Matt Arsenault, and used by RadeonSI, but it's not compatible with Vulkan. Note that AC_FLOAT_MODE_UNSAFE_FP_MATH includes the no signed zeros flag in LLVM. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* ac: set fast math flags when RADV_DEBUG="unsafemath" is usedSamuel Pitoiset2018-01-161-2/+10
| | | | | | | | When that debug option is not used, we use the default float mode because the no signed zeros optimisation is not Vulkan compatible. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* ac: import lp_create_builder() from gallivmSamuel Pitoiset2018-01-165-42/+43
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* ac: replace llvm.AMDGPU.kilp by llvm.amdgcn.kill with LLVM 6Samuel Pitoiset2018-01-161-10/+12
| | | | | | | | This also replaces llvm.AMDGPU.kilp by llvm.AMDGPU.kill with LLVM < 6. Similar to RadeonSI codepath. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* glsl/linker: link-error using the same name in unnamed block and outsideJuan A. Suarez Romero2018-01-161-0/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | According with OpenGL GLSL 4.20 spec, section 4.3.9, page 57: "It is a link-time error if any particular shader interface contains: - two different blocks, each having no instance name, and each having a member of the same name, or - a variable outside a block, and a block with no instance name, where the variable has the same name as a member in the block." This means that it is a link error if for example we have a vertex shader with the following definition. "layout(location=0) uniform Data { float a; float b; };" and a fragment shader with: "uniform float a;" As in both cases we refer to both uniforms as "a", and thus using glGetUniformLocation() wouldn't know which one we mean. This fixes KHR-GL*.shaders.uniform_block.common.name_matching. v2: add fixed tests (Tapani) Reviewed-by: Tapani Pälli <[email protected]>
* glx: fix non-dri buildSamuel Thibault2018-01-161-0/+4
| | | | | | | | | | | | | | glXGetDriverConfig parameters do not provide a context to dynamically check for the presence of the function, so the dispatcher directly calls glXGetDriverConfig, but in non-dri builds dri_glx.c didn't provide glXGetDriverConfig. This change make it just return NULL in that case. Fixes: 84f764a7591 "glxglvnddispatch: Add missing dispatch for GetDriverConfig Reviewed-by: Nicolai Hähnle <[email protected]> Reviewed-by: Hans de Goede <[email protected]> Reviewed-by: Emil Velikov <[email protected]>
* st/va: clear pointers for mpeg2 quantiser matricesIndrajit Das2018-01-161-0/+5
| | | | | | | | | This is to fix VA-API issues with GStreamer and MPEG2. Since gstreamer does not pass quantiser matrices with each frame, invalid pointers were being passed to the driver. This patch addresses the same. Signed-off-by: Indrajit Das <[email protected]> Reviewed-by: Christian König <[email protected]>
* radeon/vcn: update quantiser matrices only when requestedIndrajit Das2018-01-161-6/+11
| | | | | | | Only update them when the pointers are valid. Signed-off-by: Indrajit Das <[email protected]> Reviewed-by: Christian König <[email protected]>
* radeon/uvd: update quantiser matrices only when requestedIndrajit Das2018-01-161-6/+11
| | | | | | | Only upload them when the pointers are valid. Signed-off-by: Indrajit Das <[email protected]> Reviewed-by: Christian König <[email protected]>
* Revert "gallium/dri2: Enable {GLX_ARB,EGL_KHR}_context_flush_control"Adam Jackson2018-01-151-2/+0
| | | | | | | This reverts commit 0d044351b7043cd0bc94c1cb9b7a2213f8054414. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104490 Signed-off-by: Adam Jackson <[email protected]>
* Revert "i965: Enable flush control"Adam Jackson2018-01-152-21/+1
| | | | | | | This reverts commit 6ce9006d76c050663af0be61cc88c3215d6f8cea. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104490 Signed-off-by: Adam Jackson <[email protected]>
* Revert "ac/shader: gather If TES reads TESSINNER or TESSOUTER"Samuel Pitoiset2018-01-155-8/+4
| | | | | | | | | | | | | This can't work for two reasons: - TESSINNER/TESSOUTER are shader input values, so never translated to the intrinsic ops - the shader info pass scans the current stage but we want to know in TCS, if TES reads the tess factors. This fixes 6 regressions related to deqp-vk/tessellation/shader_input_output/tess_level_{inner,outer}_XXX_tes This reverts commit 5ba1a61648e2dea96f621a5886ad8b937a471ab4.
* amd/common: fix loading InstanceID for tess on < GFX9Samuel Pitoiset2018-01-151-2/+1
| | | | | | | | | | InstanceID is in VGPR2, not 1. One more failure that CTS didn't catch up... Reported-by: Alex Smith <[email protected]> Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* ac/shader: gather If TES reads TESSINNER or TESSOUTERSamuel Pitoiset2018-01-155-4/+8
| | | | | | | This shouldn't be scanned in the pipeline. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Timothy Arceri <[email protected]>
* ac: remove ac_shader_variant_info::fs::output_maskSamuel Pitoiset2018-01-152-3/+0
| | | | | | | Unused. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Timothy Arceri <[email protected]>
* r600/shader: Initialize max_driver_temp_used correctly for the first timeGert Wollny2018-01-151-0/+1
| | | | | | | | | | | | Without this initialization the temp registers used in tgsi_declaration may used random indices, and this may result in failing translation from TGSI with an error message "GPR limit exceeded", because the random index is greater then the allowed limit implying that the shader uses more temporary registers then available. Signed-off-by: Gert Wollny <[email protected]> Cc: <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* freedreno/ir3: "soft" depth scheduling for SFU instructionsRob Clark2018-01-141-9/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | First try with a "soft" depth, to try to schedule sfu instructions further from their consumers, but fall back to hard depth (which might result in stalling) if nothing else is avail to schedule. Previously the consumer of a sfu instruction could end up scheduled immediately after (since "hard" depth from sfu to consumer would be 0). This works because legalize pass would insert a (ss) sync bit, but it is sub-optimal since it would cause a stall. Instead prioritize other instructions for 4 cycles if they would no cause a nop to be inserted. This minimizes the stalling. There is a slight penalty in general to overall # of instructions in shader (since we could end up needing nop's later due to scheduling the "deeper" sfu consumer later), but ends up being a wash on register pressure. Overall this seems to be worth a 10+% gain in fps. Increasing the "soft" depth of sfu consumer beyond 4 helps a bit in some cases, but 4 seems to be a good trade-off between getting 99% of the gain and not increasing instruction count of shaders too much. It's possible a similar approach could help for tex/mem instructions, but the (sy) sync bit seems to trigger a switch to a different thread- group to hide memory latency (possibly with some limits depending on number of registers used?). Signed-off-by: Rob Clark <[email protected]>
* freedreno/a5xx: work around SWAP vs TILE_MODE constraintRob Clark2018-01-141-0/+20
| | | | | | | | If the blit isn't changing format, but is changing tiling, just lie and call things ARGB (since the exact component order doesn't matter for a tiling blit). Signed-off-by: Rob Clark <[email protected]>
* freedreno/a5xx: texture tilingRob Clark2018-01-1416-25/+339
| | | | | | | | | | | | | | | | | | | | | | | | | | Overall a nice 5-10% gain for most games. And more for things like glmark2 texture benchmark. There are some rough edges. In particular, the hardware seems to only support tiling or component swap. (Ie. from hw PoV, ARGB/ABGR/RGBA/ BGRA are all the same format but with different component swap.) For tiled formats, only ARGB is possible. This isn't a big problem for *sampling* since we also have swizzle state there (and since util_format_compose_swizzles() already takes into account the component order, we didn't use COLOR_SWAP for sampling). But it is a problem if you try to render to a tiled BGRA (for example) surface. The next patch introduces a workaround for blitter, so we can generate tiled textures in ABGR/RGBA/BGRA, but that doesn't help the render- target case. To handle that, I think we'd need to keep track that the tiled format is different from the linear format, which seems like it would get extra fun with sampler views/etc. So for now, disabled by default, enable with FD_MESA_DEBUG=ttile. In practice it works fine for all the games I've tried, but makes piglit grumpy. Signed-off-by: Rob Clark <[email protected]>
* freedreno: update generated headersRob Clark2018-01-146-26/+35
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno: add screen->setup_slices() for tex layoutRob Clark2018-01-143-19/+43
| | | | | | | | The rules are sufficiently different for a5xx with tiled textures, so split this out into something that can be implemented per-generation. The a5xx specific implementation will come in a later patch. Signed-off-by: Rob Clark <[email protected]>
* r300g: remove double assignmentGrazvydas Ignotas2018-01-141-1/+0
| | | | Trivial. Found by Coccinelle.
* util: use faster zlib's CRC32 implementaionGrazvydas Ignotas2018-01-141-0/+13
| | | | | | | | | | | | | | | | | | | | zlib provides a faster slice-by-4 CRC32 implementation than the traditional single byte lookup one used by mesa. As most supported platforms now link zlib unconditionally, we can easily use it. Improvement for a 1MB buffer (avg MB/s, n=100, zlib 1.2.8): i5-6600K C2D E4500 mesa zlib mesa zlib 443 1443 225% +/- 2.1% 403 1175 191% +/- 0.9% It has been verified the calculation results stay the same after this change. Signed-off-by: Grazvydas Ignotas <[email protected]> Reviewed-by: Eric Engestrom <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* util/crc32: don't drop the const qualifierGrazvydas Ignotas2018-01-141-1/+1
| | | | | | Signed-off-by: Grazvydas Ignotas <[email protected]> Reviewed-by: Eric Engestrom <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* ac: add doubles support to isignTimothy Arceri2018-01-141-7/+18
| | | | | | | | Fixes a number of int64 piglit tests, for example: generated_tests/spec/arb_gpu_shader_int64/execution/built-in-functions/fs-sign-i64vec2.shader_test Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* ac: add i64_0 and i64_1 to llvm build contextTimothy Arceri2018-01-142-0/+4
| | | | | | These will be used in the following patch. Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* ac/nir: fix translation of nir_op_b2i for doublesTimothy Arceri2018-01-141-3/+9
| | | | | | | | | | V2: just zero-extend the 32-bit value. Fixes a number of int64 piglet tests, for example: generated_tests/spec/arb_gpu_shader_int64/execution/conversion/frag-conversion-explicit-bool-int64_t.shader_test Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* ac: fix build error in si_shaderMauro Rossi2018-01-131-1/+1
| | | | | | | | | | | | | | | assert() is replaced by unreachable(), to avoid following building error: external/mesa/src/gallium/drivers/radeonsi/si_shader.c:1967:1: error: control may reach end of non-void function [-Werror,-Wreturn-type] } ^ 1 error generated. Fixes: c797cd6 ("ac: add load_patch_vertices_in() to the abi") Reviewed-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Timothy Arceri <[email protected]>
* radv/radeonsi/nir: lower 64bit flrpTimothy Arceri2018-01-132-0/+2
| | | | | | | | Fixes a bunch of arb_gpu_shader_fp64 piglit tests for example: generated_tests/spec/arb_gpu_shader_fp64/execution/built-in-functions/fs-mix-double-double-double.shader_test Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* broadcom/vc5: Use MSF to ignore discards/non-dispatched channels in loops.Eric Anholt2018-01-121-1/+5
| | | | | Prevents potential infinite loops when a non-dispatched or discarded channel never triggers the loop break condition.
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