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* glsl: use bitwise operators in varying_matches::compute_packing_class()Brian Paul2017-12-201-5/+10
* glsl: simplify loop in varying_matches::assign_locations()Brian Paul2017-12-201-5/+5
* glsl: minor simplification in assign_varying_locations()Brian Paul2017-12-201-5/+3
* glsl: make varying_matches::is_varying_packing_safe() constBrian Paul2017-12-201-2/+2
* glsl: trivial comment fixes in lower_packed_varyings.cppBrian Paul2017-12-201-1/+1
* spirv: Makefile.nir.am: include vtn_gather_types_c.py script in tarball distJuan A. Suarez Romero2017-12-201-0/+1
* st/dri: allow direct YUYV importLucas Stach2017-12-201-0/+7
* spirv: consider bitsize when handling OpSwitch casesJuan A. Suarez Romero2017-12-201-3/+11
* drirc: set allow_glsl_cross_stage_interpolation_mismatch for more gamesTapani Pälli2017-12-201-0/+8
* anv: disallow VK_REMAINING_ARRAY_LAYERS in vkCmdClearAttachments()Samuel Iglesias Gonsálvez2017-12-201-0/+2
* nvc0/ir: change textureGrad to always use lane 0 as the tex originIlia Mirkin2017-12-191-14/+46
* broadcom/vc5: Add missing setting of the UIF XOR disable flag in textures.Eric Anholt2017-12-192-0/+4
* broadcom/vc5: Clean up the comment and code around level 0 UIF.Eric Anholt2017-12-191-14/+10
* broadcom/vc5: Simplify the tiling calculations.Eric Anholt2017-12-191-49/+11
* broadcom/vc5: Return the depth in all components of depth textures.Eric Anholt2017-12-191-6/+6
* broadcom/vc5: Enable decompressing RGTC for desktop GL support.Eric Anholt2017-12-191-1/+1
* broadcom/vc5: Use u_transfer_helper for MSAA mappings.Eric Anholt2017-12-192-98/+6
* broadcom/vc5: Start adding support for rendering to Z32F_S8X24_UINT.Eric Anholt2017-12-193-5/+94
* freedreno: add debug flag to force high priority contextRob Clark2017-12-193-1/+5
* freedreno: context priority supportRob Clark2017-12-193-2/+20
* gallium: plumb context priority through to driverRob Clark2017-12-1922-2/+71
* intel/compiler/gen10: Disable push constants.Rafael Antognolli2017-12-192-0/+16
* radv: properly load unused gl_LocalInvocationID/gl_WorkGroupID componentsSamuel Pitoiset2017-12-192-5/+23
* radv: do not add extra SGPR when push constants are not usedSamuel Pitoiset2017-12-191-1/+2
* radv: change the needs_push_constants logicSamuel Pitoiset2017-12-191-4/+4
* radv: store pipeline stages that need push constantsSamuel Pitoiset2017-12-192-0/+4
* radv: remove one useless check in ac_nir_shader_info_pass()Samuel Pitoiset2017-12-191-4/+2
* radv: remove one useless check in radv_flush_constants()Samuel Pitoiset2017-12-191-1/+2
* radv: add assertions to make sure pipeline layout objects are validSamuel Pitoiset2017-12-191-0/+2
* radv: create pipeline layout objects for all meta operationsSamuel Pitoiset2017-12-194-2/+80
* radv: Use a sort for rebuilding the sparse buffer bo list.Bas Nieuwenhuizen2017-12-191-21/+24
* freedreno/ir3: handle VTXID_BASE for indirect drawsRob Clark2017-12-191-2/+41
* freedreno/ir3: add ctx->mem_to_mem()Rob Clark2017-12-194-14/+49
* freedreno/a5xx: use vertex_id_zero_baseRob Clark2017-12-192-20/+1
* r600: clear compressed flags in image state on unbind.Dave Airlie2017-12-191-0/+2
* swr: Account for index_bias in offsetsGeorge Kyriazis2017-12-181-3/+3
* r600: only reported tgsi ir compute support on evergreen+Dave Airlie2017-12-181-1/+3
* radv: Advertise sync fd import and export.Bas Nieuwenhuizen2017-12-181-4/+15
* radv: Implement sync file import/export for fences & semaphores.Bas Nieuwenhuizen2017-12-181-28/+87
* radv/amdgpu: wrap sync fd import/export.Bas Nieuwenhuizen2017-12-182-0/+26
* ac/nir: fix lds store for patch outputs.Dave Airlie2017-12-191-1/+1
* nir/linking: always set the used_across_stages/outputs_read bitsDave Airlie2017-12-191-6/+7
* spirv: Relax the validation conditions of OpSelectJason Ekstrand2017-12-181-4/+21
* radv: remove useless radv_cmask_info::base_address_regSamuel Pitoiset2017-12-181-1/+0
* amd/common: add ac_vgt_gs_mode() helperSamuel Pitoiset2017-12-184-55/+42
* amd/common: add ac_get_cb_shader_mask() helperSamuel Pitoiset2017-12-184-66/+40
* Revert "radv: do not load unused gl_LocalInvocationID/gl_WorkGroupID components"Samuel Pitoiset2017-12-181-5/+2
* radv: port merge tess info from anvDave Airlie2017-12-181-0/+40
* radv: Add external fence support.Bas Nieuwenhuizen2017-12-182-0/+22
* radv: Implement VK_KHR_external_fence_fd.Bas Nieuwenhuizen2017-12-182-0/+48
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