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* mesa: Fix trailing whitespace in polygon.cLyude2017-03-301-3/+3
| | | | | Signed-off-by: Lyude <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* mesa: Fix gross indenting in _mesa_PolygonMode()Lyude2017-03-301-5/+4
| | | | | Signed-off-by: Lyude <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* r300: Fix indenting in r300_get_param()Lyude2017-03-301-3/+3
| | | | | | Signed-off-by: Lyude <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* vc4: Fix indenting in vc4_screen_get_param()Lyude2017-03-301-3/+3
| | | | | | Signed-off-by: Lyude <[email protected]> Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* intel: Add INTEL_CFLAGS to aubinator CFLAGS.Kenneth Graunke2017-03-301-1/+2
| | | | It still needs intel_aub.h. Fixes the build.
* nir: Add support for 8 and 16-bit typesJason Ekstrand2017-03-303-2/+24
| | | | | Reviewed-by: Iago Toral Quiroga <[email protected]> Reviewed-by: Eduardo Lima Mitev <[email protected]>
* nir/constant_expressions: Don't switch on bit size when not neededJason Ekstrand2017-03-301-14/+23
| | | | | | | | | | | | For opcodes such as the nir_op_pack_64_2x32 for which all sources and destinations have explicit sizes, the bit_size parameter to the evaluate function is pointless and *should* do nothing. Previously, we were always switching on the bit_size and asserting if it isn't one of the sizes in the list. This generates way more code than needed and is a bit cruel because it doesn't let us have a bit_size of zero on an ALU op which shouldn't need a bit_size. Reviewed-by: Eduardo Lima Mitev <[email protected]>
* nir/constant_expressions: Pull the guts out into a helper blockJason Ekstrand2017-03-301-98/+101
| | | | Reviewed-by: Eduardo Lima Mitev <[email protected]>
* i965: Stop using legacy dri_bufmgr_* and intel_* names.Kenneth Graunke2017-03-3010-14/+18
| | | | | | | | Eric renamed these from dri_bufmgr_* and intel_bufmgr_* to drm_intel_* in libdrm commit 4b9826408f65976a1a13387beda748b65e03ec52, circa 2008, but we've been using the legacy names this whole time. Reviewed-by: Jason Ekstrand <[email protected]>
* intel: automake: move INTEL_CFLAGS as applicableEmil Velikov2017-03-302-1/+1
| | | | | | | | | | Only common/decoder.[ch] requires it [for intel_aub.h]. v2: The code was moved to from intel/tools to intel/common, update accordingly. Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* intel: android: remove libdrm_intel requirementEmil Velikov2017-03-303-12/+6
| | | | | | | | The only part which requires libdrm_intel tools/aubinator is not built on Android. Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* Partially revert "amd/addrlib: silence warnings" to fix builds with DEBUGMarek Olšák2017-03-303-6/+6
| | | | This partially reverts commit 8a74140a21fe6b0d2e8a60b065b890f797f2db51.
* ddebug: implement clear_textureMarek Olšák2017-03-302-0/+34
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: fix an unused-variable warning in a release buildMarek Olšák2017-03-301-3/+1
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* vdpau: fix a maybe-uninitialized warningMarek Olšák2017-03-301-1/+1
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* softpipe: fix a maybe-uninitialized warningMarek Olšák2017-03-301-1/+1
| | | | | | /home/marek/dev/mesa-main/src/gallium/drivers/softpipe/sp_compute.c:178: warning: 'grid_size' may be used uninitialized in this function [-Wmaybe-uninitialized]
* gallivm: fix a maybe-uninitialized warningMarek Olšák2017-03-301-1/+1
| | | | | | | /home/marek/dev/mesa-main/src/gallium/auxiliary/gallivm/lp_bld_sample_soa.c:3598: warning: 'level' may be used uninitialized in this function [-Wmaybe-uninitialized] out1 = lp_build_cmp(&leveli_bld, PIPE_FUNC_GREATER, level, last_level); ^
* gallium/radeon: s/dcc_disable/disable_dcc/Marek Olšák2017-03-304-9/+9
| | | | | | Reviewed-by: Nicolai Hähnle <[email protected]> Tested-by: Edmondo Tommasina <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]>
* radeonsi: handle incompatible DCC formats in resource_copy_regionMarek Olšák2017-03-301-0/+5
| | | | | | | Required because of later commits. Reviewed-by: Nicolai Hähnle <[email protected]> Tested-by: Edmondo Tommasina <[email protected]>
* radeonsi: remove a workaround for inexact *8_SNORM blitsMarek Olšák2017-03-301-3/+1
| | | | | | | | All tests pass on Fiji now. This prevents DCC disablement due to incompatible DCC formats due to the fallback. Reviewed-by: Nicolai Hähnle <[email protected]> Tested-by: Edmondo Tommasina <[email protected]>
* gallium/radeon: add and use a new helper vi_dcc_enabledMarek Olšák2017-03-305-14/+16
| | | | | | Reviewed-by: Nicolai Hähnle <[email protected]> Tested-by: Edmondo Tommasina <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]>
* gallium/radeon: formalize that r600_query_hw_add_result doesn't need a contextMarek Olšák2017-03-303-8/+9
| | | | | | Reviewed-by: Nicolai Hähnle <[email protected]> Tested-by: Edmondo Tommasina <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]>
* radeonsi: don't make a copy of pipe_index_buffer in draw_vboMarek Olšák2017-03-301-32/+27
| | | | | | Reviewed-by: Nicolai Hähnle <[email protected]> Tested-by: Edmondo Tommasina <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]>
* gallium/util: use const in u_index_modify helpersMarek Olšák2017-03-302-6/+6
| | | | | | Reviewed-by: Nicolai Hähnle <[email protected]> Tested-by: Edmondo Tommasina <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]>
* winsys/amdgpu: remove AMDGPU_INFO_NUM_EVICTIONSSamuel Pitoiset2017-03-301-4/+0
| | | | | | | | This is now exposed with libdrm_amdgpu 2.4.76. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* radeon/uvd: set correct vega10 db pitch alignmentBoyuan Zhang2017-03-301-4/+12
| | | | | | | | Create new function to get correct alignment based on Asics, and change the corresponding decode message buffer and dpb buffer size calculations Signed-off-by: Boyuan Zhang <[email protected]> Reviewed-by: Christian König <[email protected]>
* radeon/vce: add vce support for firmware 53.19.4Leo Liu2017-03-301-0/+6
| | | | | | | v2: squashed with other similar commits Signed-off-by: Leo Liu <[email protected]> Reviewed-by: Christian König <[email protected]>
* radeon/vce: adapt gfx9 surface to vceLeo Liu2017-03-302-15/+51
| | | | | | Signed-off-by: Leo Liu <[email protected]> Acked-by: Alex Deucher <[email protected]> Reviewed-by: Christian König <[email protected]>
* winsys/surface: add height pitch for gfx9Leo Liu2017-03-302-0/+2
| | | | | Signed-off-by: Leo Liu <[email protected]> Acked-by: Alex Deucher <[email protected]>
* radeon/uvd: clear message buffer when reuseLeo Liu2017-03-301-1/+2
| | | | | | | | As required by firmware Signed-off-by: Leo Liu <[email protected]> Acked-by: Alex Deucher <[email protected]> Reviewed-by: Christian König <[email protected]>
* radeon/uvd: adapt gfx9 surface to uvdLeo Liu2017-03-306-56/+106
| | | | | | Signed-off-by: Leo Liu <[email protected]> Acked-by: Alex Deucher <[email protected]> Reviewed-by: Christian König <[email protected]>
* radeon/uvd: add uvd soc15 registerLeo Liu2017-03-302-4/+27
| | | | | | Signed-off-by: Leo Liu <[email protected]> Acked-by: Alex Deucher <[email protected]> Reviewed-by: Christian König <[email protected]>
* radeonsi/gfx9: disable features that don't workMarek Olšák2017-03-304-5/+15
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi/gfx9: only allow GL 3.1Marek Olšák2017-03-301-0/+5
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi/gfx9: add linear address computations for texture transfersMarek Olšák2017-03-301-20/+53
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi/gfx9: don't generate LS and ES statesMarek Olšák2017-03-301-24/+46
| | | | | | these shaders don't exist on GFX9 Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi/gfx9: SPI_SHADER_USER_DATA changesMarek Olšák2017-03-301-11/+34
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* winsys/amdgpu: set/get BO tiling flags for GFX9Marek Olšák2017-03-301-2/+4
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi/gfx9: handle pitch and offset overrides for texture_from_handleMarek Olšák2017-03-301-11/+18
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi/gfx9: set/validate GFX9 BO metadataMarek Olšák2017-03-302-1/+24
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi/gfx9: add radeon_surf.gfx9.surf_offsetMarek Olšák2017-03-305-1/+7
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi/gfx9: don't write mipmap level offsets to BO metadataMarek Olšák2017-03-301-3/+6
| | | | | | GFX9 doesn't have (usable) mipmap offsets. Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi/gfx9: flush CB & DB caches with an EOP TS eventMarek Olšák2017-03-301-23/+84
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi/gfx9: use ACQUIRE_MEMMarek Olšák2017-03-301-6/+17
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi/gfx9: only use CE RAM for most-used descriptorsMarek Olšák2017-03-302-5/+23
| | | | | | because the CE RAM size decreased to 4 KB. Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi/gfx9: emit FLUSH_DFSM where requiredMarek Olšák2017-03-302-0/+18
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi/gfx9: emit BREAK_BATCH in emit_framebuffer_stateMarek Olšák2017-03-301-0/+5
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi/gfx9: fix MIP0_WIDTH & MIP0_HEIGHT for compressed texture blitsMarek Olšák2017-03-306-10/+26
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi/gfx9: fix textureSize/imageSize for 1D texturesMarek Olšák2017-03-301-25/+32
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi/gfx9: add a workaround for 1D depth texturesMarek Olšák2017-03-304-30/+86
| | | | | | The same workaround is used by Vulkan. Reviewed-by: Nicolai Hähnle <[email protected]>
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