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* radeon/llvm: Rename all AMDIL* classes to AMDGPU*Tom Stellard2012-07-3030-496/+496
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* radeon/llvm: Merge AMDILSubtarget into AMDGPUSubtargetTom Stellard2012-07-3025-324/+156
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* radeon/llvm: Merge AMDILTargetLowering class into AMDGPUTargetLoweringTom Stellard2012-07-3011-241/+144
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* radeon/llvm: Remove IL_cmp DAG nodeTom Stellard2012-07-304-502/+2
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* radeon/llvm: Cleanup and reorganize AMDIL .td filesTom Stellard2012-07-3013-2303/+335
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* radeon/llvm: Remove lowering code for unsupported featuresTom Stellard2012-07-308-805/+50
| | | | e.g. function calls, load/store from stack
* radeon/llvm: Remove AMDILVersion.tdTom Stellard2012-07-302-59/+0
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* radeon/llvm: Remove AMDILAlgorithms.tppTom Stellard2012-07-302-94/+19
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* radeon/llvm: Merge AMDILInstrInfo.cpp into AMDGPUInstrInfo.cppTom Stellard2012-07-3012-693/+512
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* radeon/llvm: Merge AMDILRegisterInfo into AMDGPURegisterInfoTom Stellard2012-07-3012-283/+69
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* radeon/llvm: Change the tablegen target from AMDIL to AMDGPUTom Stellard2012-07-3014-107/+119
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* i965: Support MESA_FORMAT_SIGNED_RGBA_16.Kenneth Graunke2012-07-301-1/+1
| | | | | | | | | | | | | | | | The hardware supports this format with no known quirks, so we may as well enable it. Alpha blending is not supported until Sandybridge, but as far as I can tell, OpenGL doesn't require alpha blending on SNORM formats. Plus, we already expose R8G8B8A8_SNORM which has a similar restriction. Fixes 6 piglit texwrap-2D-*SNORM* cases, gl-3.1/required-sized-texture-formats, and 10 oglconform snorm-textures subcases Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* gbm: Fix build for wayland includeElvis Lee2012-07-301-0/+1
| | | | | | backends/gbm_dri.c fails to find wayland-server.h. Signed-off-by: Elvis Lee <[email protected]>
* mesa: fix _math_matrix_copy(), againBrian Paul2012-07-301-1/+1
| | | | | The matrix is 16 GLfloats in size. Since from->inv is just a pointer (not an array), sizeof(*from->inv) wasn't right.
* mesa: Fix wrong sizeof argument in _math_matrix_copy.Vinson Lee2012-07-301-1/+1
| | | | | | | Fixes Coverity wrong sizeof argument defect. Signed-off-by: Vinson Lee <[email protected]> Signed-off-by: Brian Paul <[email protected]>
* radeonsi: fix db and stencil setup v2Christian König2012-07-303-67/+58
| | | | | | | | v2: fix tiling for small pitches, that finally makes glxgears and readPixSanity work Signed-off-by: Christian König <[email protected]> Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: fix stencil op mappingChristian König2012-07-301-40/+34
| | | | | Signed-off-by: Christian König <[email protected]> Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: fix assertion in si_bind_vs_samplerChristian König2012-07-301-1/+1
| | | | | Signed-off-by: Christian König <[email protected]> Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: fix shader bindingChristian König2012-07-301-2/+8
| | | | | Signed-off-by: Christian König <[email protected]> Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: fix dummy export in shaders v2Christian König2012-07-301-0/+19
| | | | | | | v2: add assertion for vertex shader Signed-off-by: Christian König <[email protected]> Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: fix vertex buffer and elementsChristian König2012-07-304-64/+74
| | | | | | | | Let's just use the T# descriptors until we get a fetch shader. Signed-off-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: fix shader size and handlingChristian König2012-07-301-13/+13
| | | | | | | | We should always upload the shader here. Signed-off-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: rename r600_resource to si_resourceChristian König2012-07-3015-94/+140
| | | | | | | | | Also split it into seperate header and add some helper functions. Signed-off-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Michel Dänzer <[email protected]>
* glcpp: Add a newline to expanded #line directives.Kenneth Graunke2012-07-281-2/+2
| | | | | | | | | | | | | | | | | | | | Otherwise, the preprocessor happily outputs #line 2 4 <your next line of code> and the main compiler gets horribly confused and fails to compile. This is not the right solution (line numbers in error messages will likely be off-by-one in certain circumstances), but until Carl comes up with a proper fix, this gets programs running again. Fixes regressions in Regnum Online, Overgrowth, Piglit, and others since commit aac78ce8234d96932c38b3f48b1d828077bc0027. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=51802 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=51506 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=41152 Signed-off-by: Kenneth Graunke <[email protected]>
* gallium: specify resource_resolve destination via a pipe_surfaceChristoph Bumiller2012-07-286-58/+39
| | | | | | | | | | | The format member of pipe_surface may differ from that of the pipe_resource, which is used to communicate, for instance, whether sRGB encode should be enabled in the resolve operation or not. Fixes resolve to sRGB surfaces in mesa/st when GL_FRAMEBUFFER_SRGB is disabled. Reviewed-by: Brian Paul <[email protected]>
* st/mesa: call update_renderbuffer_surface for sRGB renderbuffers, tooChristoph Bumiller2012-07-281-2/+3
| | | | | | | | | | | | sRGBEnabled should affect both textures and renderbuffers, so we need to check/update the pipe_surface format for both. Fixes, for instance, rendering appearing too bright in wine applications using sRGB multisample renderbuffers. NOTE: This is a candidate for the 8.0 branch. Reviewed-by: Brian Paul <[email protected]>
* nv50: fix depth/stencil multisample memory storage typesChristoph Bumiller2012-07-281-6/+6
| | | | Leftover from libdrm_nouveau v2 interface change.
* nv50: fix resource_resolve shader start offsetsChristoph Bumiller2012-07-281-2/+2
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* st/mesa: undo a couple static assertsBrian Paul2012-07-271-2/+2
| | | | Hmm, gcc didn't catch these mistakes, but MSVC did.
* st/mesa: use STATIC_ASSERT in a few placesBrian Paul2012-07-274-17/+17
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* mesa: whitespace, etc. fixes in program.hBrian Paul2012-07-271-7/+5
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* meta: fix glDrawPixels fallback test, stencil drawingBrian Paul2012-07-271-2/+2
| | | | | | | | | | | | | | | | | | Remove the check for pixel transfer ops. If any RGB/depth scale/bias is in effect, it'll be applied in the glTexImage step. If drawing stencil pixels we need to disable pixel transfer so that alpha scale/bias are not applied to the stencil data. These issues were spotted by Roland. Fixes Blender performance issues reported in http://bugs.freedesktop.org/show_bug.cgi?id=47375 NOTE: This is a candidate for the 8.0 branch. Tested-by: Barto <[email protected]> Reviewed-by: Roland Scheidegger <[email protected]>
* radeon: fix 'sowftware' typoBrian Paul2012-07-271-1/+1
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* i965/gen7: Reduce GT1 WM thread count according to updated BSpec.Eric Anholt2012-07-271-1/+1
| | | | | | Acked-by: Kenneth Graunke <[email protected]> https://bugs.freedesktop.org/show_bug.cgi?id=52382
* i965: Fix typo in shader channel select field name.Kenneth Graunke2012-07-273-20/+20
| | | | | | "chanel" isn't very searchable. I can type, honest! Signed-off-by: Kenneth Graunke <[email protected]>
* i965/msaa: Use MESA_FORMAT_R8 for MCS buffer.Paul Berry2012-07-271-1/+1
| | | | | | | | | | | | No functional change. This patch modifies intel_miptree_alloc_mcs to allocate the 4x MCS buffer using MESA_FORMAT_R8 instead of MESA_FORMAT_A8. In principle it doesn't matter, since we only access the buffer using MCS-specific hardware mechanisms, so all that's important is to use a format with the correct size. However, MESA_FORMAT_A8 has enough unusual behaviours that it seems prudent to avoid it. Acked-by: Kenneth Graunke <[email protected]>
* intel: increase wm thread number to 80 on gen6 GT2Zou Nan hai2012-07-271-5/+1
| | | | | | | | | | | | | It seems reset is not required for setting the max_wm_threads to 80 on gen6 GT2. Increases performance in the Counter-Strike: Source video stress test by 7.18% (n=5). Signed-off-by: Zou Nan hai <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Tested-by: Matt Turner <[email protected]> Acked-by: Eric Anholt <[email protected]>
* r600g: Emit dispatch state for compute directly to the csTom Stellard2012-07-274-69/+60
| | | | | | | We no longer rely on an evergreen_compute_resource for emitting dispatch state. Reviewed-by: Marek Olšák <[email protected]>
* r600g: Initialize VGT_PRIMITIVE_TYPE in the start_cs_cmd atomTom Stellard2012-07-271-2/+5
| | | | | | | The value of this register will always be DI_PT_POINTLIST for compute shaders. Reviewed-by: Marek Olšák <[email protected]>
* r600g: Atomize compute shader stateTom Stellard2012-07-274-86/+91
| | | | Reviewed-by: Marek Olšák <[email protected]>
* r600g: Add helper functions for emitting compute SET_CONTEXT packetsTom Stellard2012-07-272-5/+18
| | | | Reviewed-by: Marek Olšák <[email protected]>
* radeon/llvm: Add instruction defs for branches on SITom Stellard2012-07-273-17/+126
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* radeon/llvm: Fix VOPC and V_CNDMASK encodingTom Stellard2012-07-274-10/+13
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* radeon/llvm: Assert if we try to copy SCC regTom Stellard2012-07-271-0/+6
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* radeon/llvm: Add SI DAG optimizations for setcc, select_ccTom Stellard2012-07-272-0/+54
| | | | | These are needed for correctly lowering branch instructions in some cases.
* radeon/llvm: Add support for encoding SI branch instructionsTom Stellard2012-07-271-15/+35
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* radeon/llvm: Add special nodes for SALU operations on VCCTom Stellard2012-07-276-1/+89
| | | | | | | The VCC register is tricky because the SALU views it as 64-bit, but the VALU views it as 1-bit. In order to deal with this we've added some special bitcast and binary operations to help convert from the 64-bit SALU view to the 1-bit VALU view and vice versa.
* radeon/llvm: Add i1 registers for SI.Tom Stellard2012-07-271-0/+2
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* radeon/llvm: Fix CCReg definitions on SITom Stellard2012-07-272-3/+10
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* radeonsi: Enable PIPE_SHADER_CAP_INTEGERSTom Stellard2012-07-271-1/+2
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