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* radv: expose integrated device type for APUs.Dave Airlie2017-06-061-1/+1
| | | | | | | | This just sets the vulkan device type depending on whether this is an APU or GPU. Signed-off-by: Dave Airlie <[email protected]> Fixes: f4e499ec791 "radv: add initial non-conformant radv vulkan driver"
* ac/surface: Fix HTILE for radv.Bas Nieuwenhuizen2017-06-061-2/+1
| | | | | | | We always compute HTILE size using addrlib, even when not TC compatible. Signed-off-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Dave Airlied <[email protected]>
* radv: fix write event eop on vega.Dave Airlie2017-06-061-1/+1
| | | | Typo here, fixes command submission hangs on vega
* radv: enable GFX9 on radvDave Airlie2017-06-061-2/+4
| | | | | | | | I'm open to reverting this closer to release if bad things happen, but it might be easier to debugging to leave it for now. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: turn off geom/tess for gfx9.Dave Airlie2017-06-061-4/+4
| | | | | | | We don't support these yet, and it'll take a bit of work to do so. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: misc GFX9 changes.Dave Airlie2017-06-063-6/+21
| | | | | | | These are just some register changes ported from radeonsi for gfx9. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: add some GFX9 specific events.Dave Airlie2017-06-061-0/+16
| | | | | | | | These are ported from radeonsi, don't know all the rules for when they should be inserted. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: add IA_MULTI_VGT_PARAM support for GFX9.Dave Airlie2017-06-063-5/+16
| | | | | Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: add rb+ support for GFX9Dave Airlie2017-06-065-1/+22
| | | | | | | | This adds some rb+ support, as on GFX9 we have to disable it as per radeonsi. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: add GFX9 cache flushing support.Dave Airlie2017-06-064-51/+145
| | | | | | | | | GFX9 needs to write event EOP to a fence buffer, allocate some space for this, and just write an ever increasing number to it, this isn't exactly what radeonsi does, but it seems to work. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: add texture descriptor/fmask/cmask support for GFX9Dave Airlie2017-06-061-31/+158
| | | | | | | | This adds gfx9 support for the texture descriptor along with the fmask/cmask allocation routines. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: add GFX9 to initialisation cmd buffer.Dave Airlie2017-06-062-16/+61
| | | | | | | | This just adds support for initialising some GFX9 registers, and handles the different init for the VGT reuse reg. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: don't setup raster_config on gfx9.Dave Airlie2017-06-061-12/+16
| | | | | Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: add gfx9 cp dma support.Dave Airlie2017-06-061-5/+16
| | | | | | | | This adds support to the CP dma code for GFX9, ported from radeonsi. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: add gfx9 depth/stencil surface support.Dave Airlie2017-06-063-15/+74
| | | | | | | This is ported from radeonsi. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: add GFX9 support for color surfaces.Dave Airlie2017-06-063-16/+69
| | | | | | | This is ported from radeonsi. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: add some misc gfx9 pieces.Dave Airlie2017-06-066-0/+13
| | | | | | | | This just adds the strings and includes the gfx9 register defs in some files that we need them in. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: set offchip hs param like radeonsi.Dave Airlie2017-06-061-3/+1
| | | | | | | radeonsi never uses 512 here anymore. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: fix typo in comment.Dave Airlie2017-06-061-1/+1
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* radv: add a comment from radeonsi before cp dma function.Dave Airlie2017-06-061-0/+4
| | | | | | This is just copied over. Signed-off-by: Dave Airlie <[email protected]>
* radv: remove doubled up prototype.Dave Airlie2017-06-061-4/+0
| | | | Must have snuck in during a rebase.
* radv: split metadata struct into legacy/gfx9 parts.Dave Airlie2017-06-063-41/+58
| | | | | | | This is just ported from radeonsi. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: refactor some texture descriptor state.Dave Airlie2017-06-061-9/+17
| | | | | | | | This just splits out some non-gfx9 bits in advance to avoid regressions. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: refactor color surface init before gfx9.Dave Airlie2017-06-061-25/+35
| | | | | | | This just moves the code around in preparation for gfx9 support. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: refactor depth/stencil state setupDave Airlie2017-06-061-57/+62
| | | | | | | | In advance of GFX9 to reduce chances for regression, refactor this code out so adding the GFX9 changes will be more obvious. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: use radv_foreach_stage in a couple of places.Dave Airlie2017-06-061-46/+12
| | | | | | | | This just collapses a few per-stage things into a loop, shouldn't affect anything. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radeon: remove out of date LLVM_REVISION.txtEmil Velikov2017-06-052-4/+0
| | | | | | | | | | | | The file was introduced to track which LLVM revision was required, yet that has quickly gone out of shape. It has seen no updates since 2013. Cc: Nicolai Hähnle <[email protected]> Cc: Marek Olšák <[email protected]> Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Aaron Watry <[email protected]>
* gallium/u_threaded: fixes for MSVCBrian Paul2017-06-051-7/+9
| | | | | | | | | | Replace some static assertions with runtime assertions. The static asserts don't work/fail on MSVC, despite the offsets being multiples of 16 (checked with softpipe). Use correct parameter types for a few gallium context functions. Reviewed-by: Marek Olšák <[email protected]>
* r600: refactor out some compressed resource state code.Dave Airlie2017-06-061-24/+28
| | | | | | | This just takes this out to a separate function as it will get more complex with images. Reviewed-by: Glenn Kennard <[email protected]>
* r600: document some of the missing shader constants.Dave Airlie2017-06-061-0/+4
| | | | | | These are used for fragment shader thread calculations. Reviewed-by: Glenn Kennard <[email protected]>
* r600: add register info for atomic counters.Dave Airlie2017-06-062-0/+51
| | | | | | | | | The atomic counters on evergreen are implemented via append/consume UAV counters. This just adds the register info for them. The EOS packets are used to get the atomic totals extracted post shader execution for storing into a buffer. Reviewed-by: Glenn Kennard <[email protected]>
* r600: add missing RAT registers and operations.Dave Airlie2017-06-063-0/+59
| | | | | | | | | | This just documents in the headers the RAT operation list, and the RAT encoding for exports. The immediate registers are used to point to buffers for the RAT return values (_RTN instructions). Reviewed-by: Glenn Kennard <[email protected]>
* r600/sb: fix typo in field definitionsDave Airlie2017-06-061-1/+1
| | | | Pointed out by glennk.
* tgsi/scan: fix scanning fragment shaders with PrimID and Position/FaceMarek Olšák2017-06-051-7/+10
| | | | | | | | Not relevant to radeonsi, because Position/Face are system values with radeonsi, while this codepath is for drivers where Position and Face are ordinary inputs. Reviewed-by: Brian Paul <[email protected]>
* i965: Finalize miptrees before prepare_textureJason Ekstrand2017-06-051-0/+4
| | | | | | | | | In order to do resolves for texture views with different formats, we need intel_texture_object::_Format to be valid. Calling intel_finalize_mipmap_tree can safely be done multiple times in a row and should be a fairly cheap operation. Reviewed-by: Topi Pohjolainen <[email protected]>
* gallium/u_threaded: remove 16 bytes from tc_batchMarek Olšák2017-06-052-3/+0
| | | | | | All other sentinels occupy what is otherwise unused space. Reviewed-by: Samuel Pitoiset <[email protected]>
* gallium/u_threaded: align batches and call slots to 16 bytesMarek Olšák2017-06-052-3/+17
| | | | | | not sure if this helps Reviewed-by: Samuel Pitoiset <[email protected]>
* st/mesa: don't load cached TGSI shaders on demandMarek Olšák2017-06-051-1/+6
| | | | | | | | | | This fixes a performance issue with the shader cache that delayed Gallium shader create calls until draw calls. I'd like this in stable, but it's not a showstopper. Cc: 17.1 <[email protected]> Reviewed-by: Timothy Arceri <[email protected]>
* Android: use bionic pthread_barrier_* if possibleChih-Wei Huang2017-06-051-1/+1
| | | | | | | | | The pthread_barrier_* functions were introduced to bionic since Nougat. Signed-off-by: Chih-Wei Huang <[email protected]> Acked-by: Tapani Pälli <[email protected]> Acked-by: Emil Velikov <[email protected]>
* r600: fix incorrect and missing bit field in register headers.Dave Airlie2017-06-051-3/+4
| | | | | The compression field was incorrect, and we were missing the depth before shader field.
* radv: use ac_compute_surfaceNicolai Hähnle2017-06-051-386/+6
| | | | Reviewed-by: Dave Airlie <[email protected]>
* radv: prepare fmask surface creationDave Airlie2017-06-052-7/+7
| | | | | | | | | | | | | | | | | The old code copied over all the surface info from the image surface, we only want some bits of it, and to modify the flags. This prevents a regression in dEQP-VK.api.copy_and_blit.resolve_image.* and others in the subsequent switch to ac_compute_surface. v2: - also disable opt4Space in radv_amdgpu_surface, so that we can apply this patch separately *before* switching to ac_compute_surface and hopefully avoid intermittent regressions (Nicolai) Signed-off-by: Dave Airlie <[email protected]> Reviewed-by: Dave Airlie <[email protected]> Signed-off-by: Nicolai Hähnle <[email protected]>
* radv: use amdgpu_addr_createNicolai Hähnle2017-06-054-158/+5
| | | | Reviewed-by: Dave Airlie <[email protected]>
* radv: stop using radv_amdgpu_winsys::familyNicolai Hähnle2017-06-052-2/+2
| | | | Reviewed-by: Dave Airlie <[email protected]>
* radv: use ac_gpu_infoNicolai Hähnle2017-06-055-229/+13
| | | | Reviewed-by: Dave Airlie <[email protected]>
* radv: remove radeon_info::nameNicolai Hähnle2017-06-053-30/+27
| | | | Reviewed-by: Dave Airlie <[email protected]>
* radv: use ac_surface data structuresNicolai Hähnle2017-06-058-153/+81
| | | | | | | | | This is mostly mechanical changes of renaming types and introducing "legacy" everywhere. It doesn't use the ac_surface computation functions yet. Reviewed-by: Dave Airlie <[email protected]>
* radv: rename radeon_surf::bo_{size,alignment} to surf_{size,alignment}Nicolai Hähnle2017-06-053-12/+13
| | | | | | To match radeonsi / ac_surface. Reviewed-by: Dave Airlie <[email protected]>
* radv: remove unused RADEON_SURF_HAS_SBUFFER_MIPTREENicolai Hähnle2017-06-052-3/+1
| | | | Reviewed-by: Dave Airlie <[email protected]>
* radv: remove radeon_surf_level::nblk_zNicolai Hähnle2017-06-053-6/+1
| | | | | | | We're not using thick tiling modes, so we can just derive the value ourselves. Reviewed-by: Dave Airlie <[email protected]>
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