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* freedreno/ir3: implement fquantize2f16Jonathan Marek2019-10-141-0/+5
* freedreno/ir3: implement texop_texture_samplesJonathan Marek2019-10-141-5/+9
* freedreno/ir3: fix GETLOD for negative LODsJonathan Marek2019-10-141-2/+2
* freedreno/ir3: implement fdd{x,y}_coarse opcodesJonathan Marek2019-10-141-0/+2
* freedreno/ir3: increase size of inputs/outputs arraysJonathan Marek2019-10-141-2/+2
* freedreno/ir3: remove input ncomp fieldJonathan Marek2019-10-144-6/+2
* etnaviv: fix vertex buffer state emission for single stream GPUsLucas Stach2019-10-141-1/+1
* gallivm/draw/swr: make the gs_iface not depend on tgsi.Dave Airlie2019-10-154-80/+83
* iris: Implement the Gen < 9 tessellation quads workaroundKenneth Graunke2019-10-141-0/+3
* anv: Advertise VK_KHR_spirv_1_4Caio Marcelo de Oliveira Filho2019-10-141-0/+1
* vulkan: Update the XML and headers to 1.1.125Caio Marcelo de Oliveira Filho2019-10-141-5/+11
* android: amd/common: export amd/llvm headersMauro Rossi2019-10-141-0/+1
* gallium: rename PIPE_CAP_MAX_FRAMES_IN_FLIGHT to PIPE_CAP_THROTTLEJames Xiong2019-10-147-9/+7
* gallium: simplify throttle implementationJames Xiong2019-10-144-110/+13
* radv: fix DCC fast clear code for intensity formatsSamuel Pitoiset2019-10-143-9/+31
* gbm: use size_t for array indexesEric Engestrom2019-10-131-10/+5
* gbm: replace NULL sentinel with explicit ARRAY_SIZE()Eric Engestrom2019-10-131-9/+12
* gbm: replace 1/0 bool with true/falseEric Engestrom2019-10-131-8/+8
* gbm: turn 0/-1 bool into true/falseEric Engestrom2019-10-131-6/+7
* radv: add exported symbols checkEric Engestrom2019-10-131-0/+13
* anv: add exported symbols checkEric Engestrom2019-10-131-0/+13
* panfrost: Fix support for packed 24-bit formatsBoris Brezillon2019-10-131-1/+1
* glsl: fix crash compiling bindless samplers inside unnamed UBOsTimothy Arceri2019-10-121-5/+5
* glsl/builtin: Add alternate versions of atan using new opsNeil Roberts2019-10-121-2/+31
* glsl: Add opcodes for atan and atan2Neil Roberts2019-10-126-0/+31
* nir/builtin: Add extern "C" guards to nir_builtin_builder.hNeil Roberts2019-10-121-0/+8
* nir/builtin: Add #include u_math.h to the headerNeil Roberts2019-10-121-0/+1
* nir/builder: Move nir_atan and nir_atan2 from SPIR-V translatorNeil Roberts2019-10-123-153/+156
* egl: Configs w/o double buffering support have no `EGL_WINDOW_BIT`.Hal Gentz2019-10-1110-7/+78
* egl: Puts RGBA visuals in the second config selection group.Hal Gentz2019-10-111-1/+9
* egl: Fixes transparency with EGL and X11.Hal Gentz2019-10-117-17/+35
* intel/fs/gen12: Use TCS 8_PATCH mode.Kenneth Graunke2019-10-112-6/+8
* intel/fs/gen12: Implement gl_FrontFacing on gen12+.Jason Ekstrand2019-10-112-2/+25
* intel/fs/gen11+: Fix CS_OPCODE_CS_TERMINATE codegen.Francisco Jerez2019-10-112-8/+11
* intel/fs/gen12: Fix barrier codegen.Francisco Jerez2019-10-112-2/+7
* intel/eu: Don't set notify descriptor field of gateway barrier message.Francisco Jerez2019-10-111-1/+0
* intel/ir/gen12: Update assert in brw_stage_has_packed_dispatch().Francisco Jerez2019-10-111-1/+1
* intel/eu/validate/gen12: Don't blow up on indirect src0.Jason Ekstrand2019-10-111-1/+2
* intel/eu/validate/gen12: Validation fixes for SEND instruction.Francisco Jerez2019-10-111-22/+28
* intel/eu/validate/gen12: Fix validation of SYNC instruction.Francisco Jerez2019-10-111-1/+1
* intel/eu/validate/gen12: Implement integer multiply restrictions in EU valida...Francisco Jerez2019-10-111-0/+33
* intel/ir: Lower fpow on Gen12.Jordan Justen2019-10-111-0/+1
* intel/fs/gen12: Don't support source mods for 32x16 integer multiply.Francisco Jerez2019-10-111-0/+18
* intel/disasm: Disassemble register file of split SEND sources.Francisco Jerez2019-10-111-1/+4
* intel/disasm: Don't disassemble saturate control on SEND instructions.Francisco Jerez2019-10-111-2/+4
* intel/disasm/gen12: Disassemble Gen12 SEND instructions.Francisco Jerez2019-10-111-4/+18
* intel/disasm/gen12: Disassemble Gen12 SYNC instruction.Francisco Jerez2019-10-111-0/+14
* intel/disasm/gen12: Disassemble three-source instruction source and destinati...Francisco Jerez2019-10-111-13/+32
* intel/disasm/gen12: Fix disassembly of some common instruction controls.Francisco Jerez2019-10-111-4/+9
* intel/disasm/gen12: Disassemble software scoreboard information.Francisco Jerez2019-10-111-0/+16
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