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* panfrost/midgard: Implement fpowAlyssa Rosenzweig2019-03-144-1/+4
| | | | | | | We have a native op for this, which was just found in a disassembly -- so instead of lowering, use it! Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost: Compute viewport state on the flyAlyssa Rosenzweig2019-03-142-71/+38
| | | | | | | | | | | Previously, we were caching this incorrectly; there's no real reason to given how variable it is (sensitive to changes in viewport, framebuffer dimensions, and scissors) and how cheap it is to recompute. So, just do it on the fly each draw. Fixes glmark-es2 -bshadow and -brefract. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost; Disable AFBC for depth buffersAlyssa Rosenzweig2019-03-142-4/+7
| | | | | | | | | For inexplicable reasons, the depth buffer is faster if kept as linear, whereas the colour buffers are faster if AFBC. Given both code paths are available, we'll choose the faster one of each (which also helps with testing coverage). Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost: Allocate extra data for depth bufferAlyssa Rosenzweig2019-03-141-0/+5
| | | | | | | It's not clear why the hardware "spills" a little bit, but if we don't do this, we get MMU faults with linear depth buffers. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost: Comment spelling fixAlyssa Rosenzweig2019-03-141-1/+1
| | | | Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost/mfbd: Respect per-job depth write flagAlyssa Rosenzweig2019-03-144-20/+42
| | | | | | | | | | While a depth buffer may be supplied, it only needs to be written to if the depth writemask is set for any draw AND if the depth buffer is not immediately invalidated (as is the case for scanout). This refactors panfrost_job to provide a depth write requirement, which is now implemented for MFBD depth buffers. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost/mfbd: Implement linear depth buffersAlyssa Rosenzweig2019-03-141-10/+9
| | | | | | | | This removes a clunky hack where the depth buffer was enabled during the *clear*, instead of during depth buffer linking. That said, this does not yet support writeback like AFBC depth buffers. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost: Minor comment cleanup (version detection)Alyssa Rosenzweig2019-03-141-2/+3
| | | | Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost: Remove staging MFBDAlyssa Rosenzweig2019-03-142-109/+98
| | | | | | | Same idea as the previous commit, but for the MFBD this time instead of the SFBD. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost: Remove staging SFBD for pan_contextAlyssa Rosenzweig2019-03-144-39/+30
| | | | | | | | The fragment framebuffer descriptor should not be a context entry; rather, it should be constructed only at fragment time to keep analysis tractable. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost: Break out fragment to SFBD/MFBD filesAlyssa Rosenzweig2019-03-147-378/+520
| | | | | | | | This substantially cleans up the corresponding logic at the expense of a bit of code duplication; nevertheless, it's a net win since otherwise incompatible hardware code is mixed confusingly. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* freedreno: Use shared drm_find_modifier utilAlyssa Rosenzweig2019-03-141-16/+4
| | | | | Signed-off-by: Alyssa Rosenzweig <[email protected]> Reviewed-by: Rob Clark <[email protected]>
* vc4: Use shared drm_find_modifier utilAlyssa Rosenzweig2019-03-141-15/+3
| | | | | Signed-off-by: Alyssa Rosenzweig <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* v3d: Use shared drm_find_modifier utilAlyssa Rosenzweig2019-03-141-15/+3
| | | | | Signed-off-by: Alyssa Rosenzweig <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* util: Add a drm_find_modifier helperAlyssa Rosenzweig2019-03-141-0/+55
| | | | | | | | | | | | | | This function is replicated across vc4/v3d/freedreno and is needed in Panfrost; let's make this shared code. v2: Supply generic util_array_contains_u64 version (Eric Engestrom). Add missing stdbool.h include (Eric Anholt). Mark inline (Christian Gmeiner). Signed-off-by: Alyssa Rosenzweig <[email protected]> Reviewed-by: Eric Engestrom <[email protected]> Reviewed-by: Rob Clark <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* mesa: add logging function for formatted stringMark Janes2019-03-142-0/+35
| | | | Reviewed-by: Erik Faye-Lund <[email protected]>
* mesa: rename logging functions to reflect that they format stringsMark Janes2019-03-1412-92/+92
| | | | | | | In preparation for the definition of a function to log a formatted string. Reviewed-by: Erik Faye-Lund <[email protected]>
* mesa: properly report the length of truncated log messagesMark Janes2019-03-141-0/+3
| | | | | | | | | | | | | _mesa_log_msg must provide the length of the string passed into the KHR_debug api. When the string formatted by _mesa_gl_vdebugf exceeds MAX_DEBUG_MESSAGE_LENGTH, the length is incorrectly set to the number of characters that would have been written if enough space had been available. Fixes: 30256805784450b8bb9d4dabfb56226271ca9d24 ("mesa: Add support for GL_ARB_debug_output with dynamic ID allocation.") Reviewed-by: Erik Faye-Lund <[email protected]>
* anv: Only set 3DSTATE_PS::VectorMaskEnable on gen8+Jason Ekstrand2019-03-141-1/+1
| | | | | | | We don't set it on HSW and earlier in i965 and disabling it appears to make derivatives somewhat more reliable. Acked-by: Kenneth Graunke <[email protected]>
* radv: always initialize HTILE when the src layout is UNDEFINEDSamuel Pitoiset2019-03-141-2/+1
| | | | | | | | | | | | | HTILE should always be initialized when transitioning from VK_IMAGE_LAYOUT_UNDEFINED to other image layouts. Otherwise, if an app does a transition from UNDEFINED to GENERAL, the driver doesn't initialize HTILE and it tries to decompress the depth surface. For some reasons, this results in VM faults. Cc: [email protected] Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107563 Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* i965: Disable ARB_fragment_shader_interlock for platforms prior to GEN9Plamena Manolova2019-03-142-1/+25
| | | | | | | | | | | ARB_fragment_shader_interlock depends on memory fences to ensure fragment ordering and this ordering guarantee is only supported from GEN9 onwards. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=109980 Fixes: 939312702e35 "i965: Add ARB_fragment_shader_interlock support." Signed-off-by: Plamena Manolova <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* iris: Don't mutate box in transfer map codeKenneth Graunke2019-03-131-37/+28
| | | | | | | Not mutating the boxes is arguably cleaner. Split from a patch by Chris Wilson but reworked to use a pointer to the original box rather than making a copy at all.
* i965: remove scaling factors from P010, P012Tapani Pälli2019-03-141-2/+2
| | | | | | | | | | | | | | | | | | Patch removes scaling factors introduced in 2a2e69f975b but leaves option to use scaling in place as it could be useful with other upcoming YUV formats. We did this scaling because ffmpeg was shifting channel bits down, however it seems this is not the right place as compositor wants to flip same buffers directly to display as well and therefore bitshifting needs to be done by the client when receiving frame from ffmpeg. Now P0x formats are treated the same, e.g. P010 is same as P016 but with lower 6 bits set to zeros. Fixes: 2a2e69f975b "i965: add P0x formats and propagate required scaling factors" Signed-off-by: Tapani Pälli <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]>
* anv/pass: Flag the need for a RT flush for resolve attachmentsJason Ekstrand2019-03-131-1/+17
| | | | | Reviewed-by: Nanley Chery <[email protected]> Cc: [email protected]
* anv: Stop using VK_TRUE/FALSEJason Ekstrand2019-03-131-21/+21
| | | | | | | | | | | | We've been fairly inconsistent about this so we should really choose whether we're going to use VK_TRUE/FALSE or the C boolean values. The Vulkan #defines are set to 1 and 0 respectively so it's the same value as C gives you when you cast a boolean expression to an integer. Since there are several places where we set a VkBool32 to a C logical expression, let's just embrace C booleans and stop using the VK defines. Reviewed-by: Samuel Iglesias Gonsálvez <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]>
* virgl: use uint16_t mask instead of separate booleansGurchetan Singh2019-03-138-111/+106
| | | | | | | This should save some space. Suggested-by: Erik Faye-Lund <[email protected]> Reviewed-by: Emil Velikov <[email protected]>
* iris: Enable auxiliary buffer support againRafael Antognolli2019-03-131-3/+0
| | | | | | | Now that we are properly resolving buffers before giving them to the window system, let's enable aux support again. Reviewed-by: Kenneth Graunke <[email protected]>
* iris: Convert RGBX to RGBA always.Rafael Antognolli2019-03-131-14/+27
| | | | | | | | | | | In i965, we disable the use of RGBX formats, so the higher layers of Mesa choose the equivalent RGBA format, and swizzle the alpha channel to 1.0. However, Gallium won't do that. We need to explicitly convert it to RGBA. Reviewed-by: Kenneth Graunke <[email protected]>
* iris: Add resolve on iris_flush_resource.Rafael Antognolli2019-03-131-19/+19
| | | | | | | | | | | | | | The flush_resource hook is supposedly called when the resource content needs to be made visible to external (okay, that's pretty vague). For instance, it gets called before a surface gets handled to the window system. So we need to resolve it if it's not resolved yet. v2 (Ken): - Check mod_info in iris_flush_resource instead of ISL_AUX_USAGE_NONE - Drop my old broken resolve code from iris_resource_get_handle() now that Rafael's got it hooked up in the right place. Reviewed-by: Kenneth Graunke <[email protected]>
* ir3/lower_io_offsets: Try propagate SSBO's SHR into a previous shift instructionEduardo Lima Mitev2019-03-131-4/+94
| | | | | | | | | | | | | | | While we lack value range tracking, this patch tries to 'manually' propogate the division by 4 to calculate SSBO element-offset, into a possible previous shift operation (shift left or right); checking that it is safe to do so. This should help in cases like ie. when accessing a field in an array of structs, where the offset is likely defined as base plus a multiplication by a struct or array element size. See dEQP test 'dEQP-GLES31.functional.ssbo.atomic.xor.highp_uint' for an example of a shader that benefits from this. Reviewed-by: Rob Clark <[email protected]>
* ir3/compiler: Enable lower_io_offsets pass and handle new SSBO intrinsicsEduardo Lima Mitev2019-03-134-60/+59
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | These intrinsics have the offset in dwords already computed in the last source, so the change here is basically using that instead of emitting the ir3_SHR to divide the byte-offset by 4. The improvement in shader stats is significant, of up to ~15% in instruction count in some cases. Tested only on a5xx. shader-db is unfortunately not very useful here because shaders that use SSBO require GLSL versions that are not supported by freedreno yet. For examples, most Khronos CTS tests under 'dEQP-GLES31.functional.ssbo.*' are helped. A random case: dEQP-GLES31.functional.ssbo.layout.2_level_array.packed.row_major_mat3x2 with current master: ; CL prog 14/1: 1252 instructions, 0 half, 48 full ; 8 const, 8 constlen ; 61 (ss), 43 (sy) with the SSBO dword-offset moved to NIR: ; CL prog 14/1: 1053 instructions, 0 half, 45 full ; 7 const, 7 constlen ; 34 (ss), 73 (sy) The SHR previously emitted for every single SSBO instruction disappears in most cases, and the dword-offset ends up embedded in the STGB instruction as immediate in many cases as well. There are also a few of those tests that are currently failing on register allocation, that start to pass as a result of reducing the pressure. At least these, probably more: dEQP-GLES31.functional.ssbo.layout.random.unsized_arrays.24 dEQP-GLES31.functional.ssbo.layout.random.arrays_of_arrays.6 dEQP-GLES31.functional.ssbo.layout.random.arrays_of_arrays.17 dEQP-GLES31.functional.ssbo.layout.random.nested_structs_arrays.14 dEQP-GLES31.functional.ssbo.layout.random.nested_structs_arrays_instance_arrays.5 dEQP-GLES31.functional.ssbo.layout.random.nested_structs_arrays_instance_arrays.7 No regressions observed with relevant CTS and piglit tests. Reviewed-by: Rob Clark <[email protected]>
* ir3/nir: Add a new pass 'ir3_nir_lower_io_offsets'Eduardo Lima Mitev2019-03-134-0/+217
| | | | | | | | | | | | | | | | | | | | This NIR->NIR pass implements offset computations that are currently done on the IR3 backend compiler, to give NIR a better chance of optimizing them. For now, it supports lowering the dword-offset computation for SSBO instructions. It will take an SSBO intrinsic and replace it with the new ir3-specific version that adds an extra source. That source will hold the SSA value resulting from inserting a division by 4 (an SHR op) of the original byte-offset source already provided by NIR in one of the intrinsic sources. Note that on a6xx the original byte-offset is not needed, so we could potentially replace that source instead of adding a new one. But to keep things simple and consistent we always add the new source and a6xx will just ignore the original one. Reviewed-by: Rob Clark <[email protected]>
* nir: Add ir3-specific version of most SSBO intrinsicsEduardo Lima Mitev2019-03-131-0/+27
| | | | | | | | | | | These are ir3 specific versions of SSBO intrinsics that add an extra source to hold the element offset (dword), which is what the backend instructions need. The original byte-offset source provided by NIR is not replaced because on a4xx and a5xx the backend still needs it. Reviewed-by: Rob Clark <[email protected]>
* egl/dri: Avoid out of bounds array accessKevin Strasser2019-03-131-2/+4
| | | | | | | | | | | indexConfigAttrib iterates over every index in the dri driver, possibly exceeding __DRI_ATTRIB_MAX. In other words, if the dri driver has newer attributes libEGL will end up reading from uninitialized memory through dri2_to_egl_attribute_map[]. Signed-off-by: Kevin Strasser <[email protected]> Cc: [email protected] Reviewed-by: Emil Velikov <[email protected]>
* iris: Use streaming loads to read from tiled surfacesChris Wilson2019-03-132-2/+5
| | | | | | | | | | | Always use the streaming load (since we know we have Broadwell+, all of our target CPU support sse41) for reading back form the tiled surface for mapping the resource. This means we hit the fast WC handling paths on Atoms (without LLC), and for big Core (with LLC) using the streaming load is no less efficient as we do not require the tiled buffer to be pulled into the CPU cache. Reviewed-by: Kenneth Graunke <[email protected]>
* iris: Use coherent allocation for PIPE_RESOURCE_STAGINGChris Wilson2019-03-133-1/+24
| | | | | | | | | On !llc machines (Atoms), reading from a linear buffers is slow and so copying from one resource into the linear staging buffer is still slow. However, we can tell the GPU to snoop the CPU cache when reading from and writing to the staging buffer eliminating the slow uncached reads. Reviewed-by: Kenneth Graunke <[email protected]>
* iris: Use PIPE_BUFFER_STAGING for the query objectsChris Wilson2019-03-131-1/+1
| | | | | | We prefer fast CPU access to read back the query results. Reviewed-by: Kenneth Graunke <[email protected]>
* intel/nir: Combine store_derefs to improve code from SPIR-VCaio Marcelo de Oliveira Filho2019-03-131-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Due to lack of write mask in SPIR-V store, generators may produce multiple stores to the same vector but using different array derefs. Use the combining store pass to clean this up. For example, layout(binding = 3) buffer block { vec4 v; }; void main() { v.x = 11; v.y = 22; } after going to SPIR-V and NIR, ends up with in two store_derefs to v[0] and v[1] vec2 32 ssa_4 = deref_struct &ssa_3->field0 (ssbo vec4) /* &((block *)ssa_2)->field0 */ vec2 32 ssa_6 = deref_array &(*ssa_4)[0] (ssbo float) /* &((block *)ssa_2)->field0[0] */ intrinsic store_deref (ssa_6, ssa_7) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_13 = load_const (0x00000001 /* 0.000000 */) vec2 32 ssa_14 = deref_array &(*ssa_4)[1] (ssbo float) /* &((block *)ssa_2)->field0[1] */ intrinsic store_deref (ssa_14, ssa_15) (1, 0) /* wrmask=x */ /* access=0 */ producing two different sends instructions in skl. The combining pass transform the snippet above into vec2 32 ssa_4 = deref_struct &ssa_3->field0 (ssbo vec4) /* &((block *)ssa_2)->field0 */ vec4 32 ssa_18 = vec4 ssa_7, ssa_15, ssa_16, ssa_17 intrinsic store_deref (ssa_4, ssa_18) (3, 0) /* wrmask=xy */ /* access=0 */ producing a single sends instruction. v2: Move this from spirv_to_nir into the general optimization pass for intel compiler. (Jason) Reviewed-by: Jason Ekstrand <[email protected]>
* intel/nir: Combine store_derefs after vectorizing IOCaio Marcelo de Oliveira Filho2019-03-131-0/+1
| | | | | | | | | | | | | | | | | | Shader-db results for skl: total instructions in shared programs: 15232903 -> 15224781 (-0.05%) instructions in affected programs: 61246 -> 53124 (-13.26%) helped: 221 HURT: 0 total cycles in shared programs: 371440470 -> 371398018 (-0.01%) cycles in affected programs: 281363 -> 238911 (-15.09%) helped: 221 HURT: 0 Results for bdw are very similar. Reviewed-by: Jason Ekstrand <[email protected]>
* nir: Add a pass to combine store_derefs to same vectorCaio Marcelo de Oliveira Filho2019-03-136-0/+580
| | | | | | | | | v2: (all from Jason) Reuse existing function for the end of the block combinations. Check the SSA values are coming from the right place in tests. Document the case when the store to array_deref is reused. Reviewed-by: Jason Ekstrand <[email protected]>
* ac: use the raw tbuffer version for 16-bit SSBO loadsSamuel Pitoiset2019-03-133-6/+3
| | | | | | | vindex is always 0. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* ac: add ac_build_{struct,raw}_tbuffer_load() helpersSamuel Pitoiset2019-03-133-23/+75
| | | | | | | The struct version sets IDXEN=1, while the raw version sets IDXEN=0. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: use typed buffer loads for vertex input fetchesSamuel Pitoiset2019-03-134-53/+57
| | | | | | | | | | | | | | | | | | | | | | | | | | This drastically reduces the number of SGPRs because the driver now uses descriptors per vertex binding, instead of per vertex attribute format. 29077 shaders in 15096 tests Totals: SGPRS: 1354285 -> 1282109 (-5.33 %) VGPRS: 909896 -> 908800 (-0.12 %) Spilled SGPRs: 24840 -> 24811 (-0.12 %) Code Size: 49221144 -> 48986628 (-0.48 %) bytes Max Waves: 243930 -> 244229 (0.12 %) Totals from affected shaders: SGPRS: 390648 -> 318472 (-18.48 %) VGPRS: 288432 -> 287336 (-0.38 %) Spilled SGPRs: 94 -> 65 (-30.85 %) Code Size: 11548412 -> 11313896 (-2.03 %) bytes Max Waves: 86460 -> 86759 (0.35 %) This gives a really tiny boost. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: store more vertex attribute infos as pipeline keysSamuel Pitoiset2019-03-133-0/+37
| | | | | | | They are required for using typed buffer loads. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* ac: rework typed buffers loads for LLVM 7Samuel Pitoiset2019-03-133-57/+83
| | | | | | | Be more generic, this will be used by an upcoming series. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* panfrost: Set bo->gem_handle when creating a linear BOTomeu Vizoso2019-03-131-1/+3
| | | | | | | So we can free it later. Signed-off-by: Tomeu Vizoso <[email protected]> Reviewed-by: Alyssa Rosenzweig <[email protected]>
* panfrost: Set bo->size[0] in the DRM backendTomeu Vizoso2019-03-131-5/+5
| | | | | | | So we can unmap it later. Signed-off-by: Tomeu Vizoso <[email protected]> Reviewed-by: Alyssa Rosenzweig <[email protected]>
* intel/fs: Fix opt_peephole_csel to not throw away saturates.Kenneth Graunke2019-03-121-0/+1
| | | | | | | | | | | | | | | | We were not copying the saturate bit from the original instruction to the new replacement instruction. This caused major misrendering in DiRT Rally on iris, where comparisons leading to discards failed due to the missing saturate, causing lots of extra garbage pixels to be drawn in text rendering, trees, and so on. This did not show up on i965 because st/nir performs a more aggressive version of nir_opt_peephole_select, yielding more b32csel operations. Fixes: 52c7df1643e i965/fs: Merge CMP and SEL into CSEL on Gen8+ Reviewed-by: Lionel Landwerlin <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* glsl/lower_vector_derefs: Don't use a temporary for TCS outputsJason Ekstrand2019-03-131-10/+64
| | | | | | | | | | | | Tessellation control shader outputs act as if they have memory backing them and you can have multiple writes to different components of the same vector in-flight at the same time. When this happens, the load vec store pattern that gets used by ir_triop_vector_insert doesn't yield the correct results. Instead, just emit a sequence of conditional assignments. Reviewed-by: Ian Romanick <[email protected]> Cc: [email protected]
* glsl/list: Add a list variant of insert_afterJason Ekstrand2019-03-131-0/+26
| | | | | Reviewed-by: Ian Romanick <[email protected]> Caio Marcelo de Oliveira Filho <[email protected]>
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