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* intel/vec4: Fix nir_op_b2[fi] with 64-bit resultJason Ekstrand2018-10-111-1/+6
| | | | | | | | | This is valid NIR but you can't actually hit this case today. GLSL IR doesn't have a bool to double opcode; it does f2d(b2f(x)). In SPIR-V we don't have any to/from bool conversion opcodes at all. However, the next commit will make us start generating it so we should be ready. Reviewed-by: Ian Romanick <[email protected]>
* intel/fs: Fix nir_op_b2[fi] with 64-bit result on Gen8 LP and Gen9 LPJason Ekstrand2018-10-111-5/+5
| | | | | | | | | | | | | | | | | | | | | | Several of the Atom GPUs have additional restrictions on alignment when moving < 64-bit source to a 64-bit destination. All of the nir_op_*2*64 code generation paths respected this, but nir_op_b2[fi] did not. Previous to commit a68dd47b911 it was not possible to generate such an instruction from the GLSL path. It may have been possible from SPIR-V, but it's not clear. The aforementioned patch converts a 64-bit nir_op_fsign into a sequence of operations including a nir_op_b2f with a 64-bit result. This "just works" everywhere except these Atom parts. This problem was not detected during normal CI testing because the Atom parts are not included in developer builds. v2 (idr): Make the patch compile, and make some cosmetic changes. Add a commit message. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108319 Fixes: a68dd47b911 "nir/algebraic: Simplify fsat of fsign" Reviewed-by: Ian Romanick <[email protected]>
* egl: Use correct shared libraries suffix on macOS.Vinson Lee2018-10-111-1/+6
| | | | | Signed-off-by: Vinson Lee <[email protected]> Reviewed-by: Eric Engestrom <[email protected]>
* mesa: Fix pack_uint_Z_FLOAT32()Illia Iorin2018-10-112-18/+9
| | | | | | | | | | | | Fixed pack_uint_Z_FLOAT32 by casting row data to float instead uint. Remove code duplicate function pack_uint_Z_FLOAT32_X24S8. Edited case in "_mesa_get_pack_uint_z_func". Now it looks like "_mesa_get_pack_float_z_func". Remove _mesa_problem call, which was added for debuging this issue. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91433 Signed-off-by: Illia Iorin <[email protected]> Reviewed-by: Nanley Chery <[email protected]>
* intel: Introducing Whiskey Lake platformRodrigo Vivi2018-10-113-1/+3
| | | | | | | | | | | | | | | | | | | Whiskey Lake uses the same gen graphics as Coffe Lake, including some ids that were previously marked as reserved on Coffe Lake, but that now are moved to WHL page. This follows the ids and approach used on kernel's commit b9be78531d27 ("drm/i915/whl: Introducing Whiskey Lake platform") and commit c1c8f6fa731b ("drm/i915: Redefine some Whiskey Lake SKUs") v2: Lionel noticed that GT{1,2,3} on kernel wasn't following spec when looking to number of EUs, so kernel has been updated. Cc: Lionel Landwerlin <[email protected]> Cc: José Roberto de Souza <[email protected]> Cc: Anuj Phogat <[email protected]> Signed-off-by: Rodrigo Vivi <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]>
* st/va: use provided sizes and coords for vlVaGetImageBoyuan Zhang2018-10-111-3/+28
| | | | | | | | | | | | | | | | vlVaGetImage should respect the width, height, and coordinates x and y that passed in. Therefore, pipe_box should be created with the passed in values instead of surface width/height. v2: add input size check, return error when size out of bounds v3: fix the size check for vaimage v4: add size adjustment for x and y coordinates Signed-off-by: Boyuan Zhang <[email protected]> Cc: "18.2" <[email protected]> Reviewed-by: Leo Liu <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]> Acked-by: Christian König <[email protected]>
* radv: implement clear operations for R32G32B32Samuel Pitoiset2018-10-113-1/+284
| | | | | | | | | | This fixes crashes for some CTS: dEQP-VK.api.copy_and_blit.core.blit_image.all_formats.color.*.linear_*_* dEQP-VK.api.copy_and_blit.core.blit_image.all_formats.color.*.*_linear_* Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108113 Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: disallow 3D images and mipmaps/layers for R32G32B32 linear formatsSamuel Pitoiset2018-10-111-0/+14
| | | | | | | | R32G32B32 are weird formats and we are only going to support some basic operations for now. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: add a workaround for a VGT hang with prim restart and stripsSamuel Pitoiset2018-10-111-0/+11
| | | | | | | | | | | Otherwise, Yakuza and The Evil Within hang the GPU with DXVK. This apparently only works on Polaris. Suggested by Marek. Cc: [email protected] Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* glsl: remove redundant es_shader checksTimothy Arceri2018-10-112-5/+1
| | | | | | The es check is already covered by the is_version() check. Reviewed-by: Ian Romanick <[email protected]>
* st/glsl_to_tgsi: initialise need_uarl in contructorDave Airlie2018-10-111-0/+1
| | | | | | Found by coverity Reviewed-by: Marek Olšák <[email protected]>
* glspirv: drop pointless assert (size_t is unsigned)Dave Airlie2018-10-111-2/+0
| | | | | | Found by coverity Reviewed-by: Alejandro Piñeiro <[email protected]>
* radv: remove unsigned comparison against 0Dave Airlie2018-10-111-1/+1
| | | | | | | | The value is always >= 0 here. Found by coverity Reviewed-by: Samuel Pitoiset <[email protected]>
* radv: remove dead code for master_fd closeDave Airlie2018-10-111-2/+0
| | | | | | | | | We have never opened master_Fd at this point, so remove code to close it. Found by coverity. Reviewed-by: Samuel Pitoiset <[email protected]>
* radv: don't pass shader key by copyDave Airlie2018-10-111-7/+6
| | | | | | Coverity pointed out we were copying 168 bytes here unnecessarily. Reviewed-by: Samuel Pitoiset <[email protected]>
* anv: add missing unlock in error path.Dave Airlie2018-10-111-0/+1
| | | | | | | | | | Not going to matter, but be consistent. Found by coverity Reviewed-by: Lionel Landwerlin <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Fixes: caf41c78c (anv/allocator: Support softpin in the BO cache)
* intel: Don't propagate conditional modifiers if a UD source is negatedJason Ekstrand2018-10-105-0/+50
| | | | | | | | | This fixes a bug uncovered by my NIR integer division by constant optimization series. Fixes: 19f9cb72c8b "i965/fs: Add pass to propagate conditional..." Fixes: 627f94b72e0 "i965/vec4: adding vec4_cmod_propagation..." Reviewed-by: Ian Romanick <[email protected]>
* util: Add tests for fast integer division by constantsJason Ekstrand2018-10-104-0/+546
| | | | | | | | | While I generally trust rediculousfish to have done his homework, we've made some adjustments to suit the needs of mesa and it'd be good to test those. Also, there's no better place than unit tests to clearly document the different edge cases of the different methods. Reviewed-by: Marek Olšák <[email protected]>
* util: Add power-of-two divisor support to compute_fast_udiv_infoMarek Olšák2018-10-102-2/+23
| | | | | Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* util: Generalize fast integer division to be variable bit-widthJason Ekstrand2018-10-102-45/+39
| | | | | | | | | | | | | | | There's nothing inherently fixed-width in the code. All that's required to generalize it is to make everything internally 64-bit and pass UINT_BITS in as a parameter to util_compute_fast_[us]div_info. With that, it can now handle 8, 16, 32, and 64-bit integer division by a constant. We also add support for division by 1 and by other powers of 2. This is useful if you want to divide by a uniform value in a shader where you have the opportunity to adjust the uniform on the CPU before passing it in. Reviewed-by: Marek Olšák <[email protected]>
* util: Add fast division helpersMarek Olšák2018-10-101-0/+44
| | | | Reviewed-by: Jason Ekstrand <[email protected]>
* util: import public domain code for integer division by a constantMarek Olšák2018-10-104-0/+365
| | | | | | | | | | | | | Compilers can use this to generate optimal code for integer division by a constant. Additionally, an unsigned division by a uniform that is constant but not known at compile time can still be optimized by passing 2-4 division factors to the shader as uniforms and executing one of the fast_udiv* variants. The signed division algorithm doesn't have this capability. Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* util: Add a simple big math libraryJason Ekstrand2018-10-104-0/+115
| | | | Reviewed-by: Ian Romanick <[email protected]>
* glsl: ignore trailing whitespace when define redefinedTimothy Arceri2018-10-103-3/+25
| | | | | | | | | The Nvidia/AMD binary drivers allow this, as does GCC. This fixes shader compilation issues in the latest update of No Mans Sky. Reviewed-by: Ian Romanick <[email protected]>
* intel/compiler: Don't handle fsign.satIan Romanick2018-10-092-23/+3
| | | | | | | No shader-db or CI changes on any Intel platform. Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Thomas Helland <[email protected]>
* nir/algebraic: Simplify fsat of fsignIan Romanick2018-10-091-0/+1
| | | | | | | | | | These allows us to not support fsign.sat in the Intel compiler backend, and that will simplify some later changes. No shader-db changes on any Intel platform. Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Thomas Helland <[email protected]>
* nir/algebraic: sign(x)*x*x is abs(x)*xIan Romanick2018-10-091-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | shader-db results: All Gen7+ platforms had similar results. (Skylake shown) total instructions in shared programs: 15106023 -> 15105981 (<.01%) instructions in affected programs: 300 -> 258 (-14.00%) helped: 6 HURT: 0 helped stats (abs) min: 7 max: 7 x̄: 7.00 x̃: 7 helped stats (rel) min: 14.00% max: 14.00% x̄: 14.00% x̃: 14.00% 95% mean confidence interval for instructions value: -7.00 -7.00 95% mean confidence interval for instructions %-change: -14.00% -14.00% Instructions are helped. total cycles in shared programs: 566050327 -> 566050075 (<.01%) cycles in affected programs: 2826 -> 2574 (-8.92%) helped: 6 HURT: 0 helped stats (abs) min: 40 max: 44 x̄: 42.00 x̃: 42 helped stats (rel) min: 8.89% max: 8.94% x̄: 8.92% x̃: 8.92% 95% mean confidence interval for cycles value: -44.30 -39.70 95% mean confidence interval for cycles %-change: -8.95% -8.88% Cycles are helped. No changes on Gen6 or earlier. Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Thomas Helland <[email protected]>
* nir: Add helper functions to get the instruction that generated a nir_srcIan Romanick2018-10-091-0/+23
| | | | | Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Thomas Helland <[email protected]>
* svga: change svga_destroy_shader_variant() to return voidBrian Paul2018-10-095-23/+6
| | | | | | | | | | | | | svga_destroy_shader_variant() itself flushes and retries the command if there's a failure. So no need for the callers to do it. Other callers of the function were already ignoring the return value. This also fixes a corner-case double-free reported by Coverity (and reported by Dave Airlie). Tested with various OpenGL apps. Reviewed-by: Charmaine Lee <[email protected]>
* meson: Don't build glsl compiler tests unless OpenGL is enabledDylan Baker2018-10-092-2/+2
| | | | | | Since there are no other users of the glsl compiler. Reviewed-by: Eric Engestrom <[email protected]>
* meson: Only build gallium state tracker tests with shared_glapiDylan Baker2018-10-091-1/+1
| | | | | | | This has always been a requirement, it's just somehow been missed in the meson build. Reviewed-by: Eric Engestrom <[email protected]>
* meson: only build clapi tests when OpenGL is being builtDylan Baker2018-10-092-2/+2
| | | | | | | | Otherwise building just vulkan (among other things) will build these tests, pull in a bunch of stuff they shouldn't, and potentially fail to compile. Reviewed-by: Eric Engestrom <[email protected]>
* nvc0: fix blitting red to srgb8_alphaIlia Mirkin2018-10-091-0/+4
| | | | | | | | | | | | | For some reason the 2d engine can't handle this. Red formats get special treatment there, so perhaps related. Fixes dEQP-GLES3 tests of the form: dEQP-GLES3.functional.fbo.blit.conversion.r{8,16f,32f}_to_srgb8_alpha8 Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Karol Herbst <[email protected]> Cc: [email protected]
* nv50,nvc0: guard against zero-size blitsIlia Mirkin2018-10-092-0/+14
| | | | | | | | | | The current state tracker can generate these sometimes. Fixing this is more involved, and due to some integer math we can generate divisions-by-zero. Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Karol Herbst <[email protected]> Cc: [email protected]
* nv50,nvc0: mark RGBX_UINT formats as renderableIlia Mirkin2018-10-091-4/+4
| | | | | | | | | | | | | | | | This helps st/mesa avoid some (apparently) buggy fallbacks. Specifically the CopyTexSubImage fallback tries to read texture A as RGBA_FLOAT and write back that data into the target format, which fails for integer formats which have no appropriate logic to do the conversion. Since integer formats don't blend, there's no harm in the fact that the "A" component gets written anyways. Fixes, among others: https://www.khronos.org/registry/webgl/sdk/tests/conformance2/textures/canvas/tex-2d-rgb8ui-rgb_integer-unsigned_byte.html Signed-off-by: Ilia Mirkin <[email protected]> Cc: [email protected]
* radv: add missing meson c++ visibility argumentsEric Engestrom2018-10-091-0/+1
| | | | | | | | Fixes: 6f3aee40f90d725653b6 "radv: using tls to store llvm related info and speed up compiles (v10)" Cc: Dave Airlie <[email protected]> Signed-off-by: Eric Engestrom <[email protected]> Reviewed-by: Dylan Baker <[email protected]>
* gbm: Add GBM_FORMAT_ARGB1555 supportMichel Dänzer2018-10-091-0/+4
| | | | Reviewed-by: Marek Olšák <[email protected]>
* st/dri: Handle BGRA5551 formatMichel Dänzer2018-10-091-0/+13
| | | | Reviewed-by: Marek Olšák <[email protected]>
* freedreno/a5xx+a6xx: fix LRZ pitch alignmentRob Clark2018-10-081-1/+1
| | | | | | | Both RB_2D_DST_SIZE.PITCH (a6xx) and RB_MRT[n].PITCH (a5xx) need alignment to 64. Signed-off-by: Rob Clark <[email protected]>
* freedreno/a6xx: add LRZ supportRob Clark2018-10-088-132/+104
| | | | | | | | | | As with a5xx, hidden behind FD_MESA_DEBUG=lrz due to being paranoid about z-fighting issues with some games (in particular, this was observed with 0ad on a5xx.. but I think the proper solution to enable this by default is to figure out how to do driver specific driconf options). Signed-off-by: Rob Clark <[email protected]>
* freedreno: update generated headersRob Clark2018-10-087-38/+120
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/a6xx: add helper for various CP_EVENT_WRITERob Clark2018-10-085-38/+30
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/a6xx: remove unused fxnsRob Clark2018-10-082-19/+0
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/a6xx: remove fd6_shader_stateobjRob Clark2018-10-083-23/+10
| | | | | | | Earlier gen's already got this cleanup, but a6xx was still off on a branch then. Signed-off-by: Rob Clark <[email protected]>
* glsl: fix array assignments of a swizzled vectorIlia Mirkin2018-10-081-3/+10
| | | | | | | | | | | | | | | | | | | | | | | | This happens in situations where we might do vec.wzyx[i] = ... The swizzle would get effectively ignored because of the interaction between how ir_assignment->set_lhs works and overwriting the write_mask. There are two cases, one where i is a constant, and another where i is variable. We have to be extra-careful in both cases. Fixes the following WebGL test: https://www.khronos.org/registry/webgl/sdk/tests/conformance2/glsl3/vector-dynamic-indexing-swizzled-lvalue.html And the new piglit tests: swizzled-writemask-indexing-nonconst.shader_test swizzled-writemask-indexing.shader_test Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Ian Romanick <[email protected]> Cc: [email protected]
* radv: tidy up radv_pipeline_init_multisample_state()Samuel Pitoiset2018-10-081-19/+16
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: always set PA_SC_MODE_CNTL_1.OUT_OF_ORDER_WATER_MARKSamuel Pitoiset2018-10-081-2/+2
| | | | | | | | It has probably no effect without out of order rasterization anyway. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: set DB_EQAA.INCOHERENT_EQAA_READSSamuel Pitoiset2018-10-081-1/+1
| | | | | | | | My attempt was to set this field instead of duplicating one. Fixes: 6cfa321c39 ("radv: add potential missing fields for DB_EQAA") Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* i965: fallback RGBX to RGBA in glEGLImageTargetRenderbufferStorageOESChystiakov, Dmytro2018-10-081-26/+37
| | | | | | | | | | | | | | | In the same fashion as is done for glEGLImageTextureTarget2D. v2: share the fallback which sets baseformat and internalformat correctly which makes both of the tests pass (Tapani) Fixes android.hardware.nativehardware.cts.AHardwareBufferNativeTests: #SingleLayer_ColorTest_GpuColorOutputCpuRead_R8G8B8X8_UNORM #SingleLayer_ColorTest_GpuColorOutputIsRenderable_R8G8B8X8_UNORM Signed-off-by: Tapani Pälli <[email protected]> Reviewed-by: Gurchetan Singh <[email protected]>
* glsl: do not attempt assignment if operand type not parsed correctlyTapani Pälli2018-10-081-0/+6
| | | | | | | | | v2: check types of both operands (Ian) Cc: [email protected] Signed-off-by: Tapani Pälli <[email protected]> Reviewed-by: Ian Romanick <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108012
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