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* i965/fs: Allow copy propagation on ATTR file registers.Kenneth Graunke2015-05-061-1/+4
| | | | | | | | | | | | | | | | | | | | | | This especially helps with NIR because we currently emit MOVs at the top of the shader to copy from various ATTR registers to a giant VGRF array of all inputs. (This could potentially be done better, but since there's only ever one write to each register, it should be trivial to copy propagate away...) With NIR - only vertex shaders: total instructions in shared programs: 3129373 -> 2889581 (-7.66%) instructions in affected programs: 3119717 -> 2879925 (-7.69%) helped: 20833 Without NIR - only vertex shaders: total instructions in shared programs: 2745901 -> 2724483 (-0.78%) instructions in affected programs: 693426 -> 672008 (-3.09%) helped: 3516 Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* i965/fs_inst: Get rid of the effective_width fieldJason Ekstrand2015-05-063-37/+3
| | | | | | | | The effective_width field was an ill-concieved hack to get around issues in the LOAD_PAYLOAD instruction. Now that the LOAD_PAYLOAD instruction is far more sane, this field can die. Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: Rework the fs_visitor LOAD_PAYLOAD instructionJason Ekstrand2015-05-064-236/+179
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The newly reworked instruction is far more straightforward than the original. Before, the LOAD_PAYLOAD instruction was lowered by a the complicated and broken-by-design pile of heuristics to try and guess force_writemask_all, exec_size, and a number of other factors on the sources. Instead, we use the header_size on the instruction to denote which sources are "header sources". Header sources are required to be a single physical hardware register that is copied verbatim. The registers that follow are considered the actual payload registers and have a width that correspond's to the LOAD_PAYLOAD's exec_size and are treated as being per-channel. This gives us a fairly straightforward lowering: 1) All header sources are copied directly using force_writemask_all and, since they are guaranteed to be a single register, there are no force_sechalf issues. 2) All non-header sources are copied using the exact same force_sechalf and force_writemask_all modifiers as the LOAD_PAYLOAD operation itself. 3) In order to accommodate older gens that need interleaved colors, lower_load_payload detects when the destination is a COMPR4 register and automatically interleaves the non-header sources. The lower_load_payload pass does the right thing here regardless of whether or not the hardware actually supports COMPR4. This patch commit itself is made up of a bunch of smaller changes squashed together. Individual change descriptions follow: i965/fs: Rework fs_visitor::LOAD_PAYLOAD We rework LOAD_PAYLOAD to verify that all of the sources that count as headers are, indeed, exactly one register and that all of the non-header sources match the destination width. We then take the exec_size for LOAD_PAYLOAD directly from the destination width. i965/fs: Make destinations of load_payload have the appropreate width i965/fs: Rework fs_visitor::lower_load_payload v2: Don't allow the saturate flag on LOAD_PAYLOAD instructions i965/fs_cse: Support the new-style LOAD_PAYLOAD i965/fs_inst::is_copy_payload: Support the new-style LOAD_PAYLOAD i965/fs: Simplify setup_color_payload Previously, setup_color_payload was a a big helper function that did a lot of gen-specific special casing for setting up the color sources of the LOAD_PAYLOAD instruction. Now that lower_load_payload is much more sane, most of that complexity isn't needed anymore. Instead, we can do a simple fixup pass for color clamps and then just stash sources directly in the LOAD_PAYLOAD. We can trust lower_load_payload to do the right thing with respect to COMPR4. Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: Make LOAD_PAYLOAD take a header sizeJason Ekstrand2015-05-064-12/+20
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: Make emit_single_fb_write take an explicit exec_sizeJason Ekstrand2015-05-062-8/+10
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs_inst: Add an is_copy_payload helperJason Ekstrand2015-05-064-35/+25
| | | | | | | | | | This commit adds a new is_copy_payload helper to fs_inst that takes the place of the similarly named functions in cse and register coalesce. The two is_copy_payload functions in CSE and register coalesce were subtly different and potentially subtly broken. The new version unifies the two and should be more correct. Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Change header_present to header_size in backend_instructionJason Ekstrand2015-05-069-52/+56
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs_cse: Factor out code to create copy instructionsJason Ekstrand2015-05-061-37/+38
| | | | | | | | v2: Get rid of the block parameter and make src a const reference Reviewed-by: Topi Pohjolainen <[email protected]> Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: Make half(fs_reg, unsigned) handle register files more explicitlyJason Ekstrand2015-05-061-5/+16
| | | | | | | | | Previously, we had a special case for uniforms and immediates and then a bunch of asserts for various other pessimal things. This commit changes it so that it explicitly does something on each register file. Some of them are disallowed and others are treated properly. Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: Fix passing an immediate to half().Francisco Jerez2015-05-061-2/+2
| | | | | | | Immediates are generally uniform, they yield the same value to both halves of any instruction. Reviewed-by: Matt Turner <[email protected]>
* swrast: Build fix for darwinJeremy Huddleston Sequoia2015-05-061-0/+16
| | | | | | | | | | | Fixes regression from commit 64b1dc44495890cbc2c7c5509cb830264020998c Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90147 Signed-off-by: Jeremy Huddleston Sequoia <[email protected]> Reviewed-by: Brian Paul <[email protected]> CC: Emil Velikov <[email protected]> CC: [email protected] CC: [email protected]
* egl/dri2: Check return value of __DRI2fence::create_fence()Chad Versace2015-05-061-0/+7
| | | | | | If it returns NULL, then return early with an error. Reviewed-by: Marek Olšák <[email protected]>
* draw: (trivial) fix out-of-bounds vector initializationRoland Scheidegger2015-05-061-1/+1
| | | | | | | | | | | | Was off-by-one. llvm says inserting an element with an index higher than the number of elements yields undefined results. Previously such inserts were ignored but as of llvm revision 235854 the vector gets replaced with undef, causing failures. This fixes piglit gl-3.2-layered-rendering-gl-layer, as mentioned in https://llvm.org/bugs/show_bug.cgi?id=23424. Reviewed-by: Brian Paul <[email protected]> Cc: [email protected]
* main/queryobj: add GL_QUERY_TARGET support to GetQueryObjectiv()Martin Peres2015-05-061-0/+12
| | | | | | | | This was missing from my patchset to support the query-related entry points of Direct State Access. Reported-by: Ilia Mirkin <[email protected]> Signed-off-by: Martin Peres <[email protected]>
* ilo: silence a compiler warningChia-I Wu2015-05-061-1/+1
| | | | | | | | Silence ilo_query.c:120:7: warning: 'return' with no value, in function returning non-void since commit 96f164f6.
* mesa: support compute stage in _mesa_program_resource_propTapani Pälli2015-05-061-6/+16
| | | | | | | | | | Increases pass rate of ES31-CTS.*program_interface_query* tests when run with MESA_EXTENSION_OVERRIDE='GL_ARB_compute_shader'. Many of the negative tests that happen to use compute stage in queries start passing. Signed-off-by: Tapani Pälli <[email protected]> Reviewed-by: Martin Peres <[email protected]>
* glsl: mark special built-in inputs referenced by vertex stageTapani Pälli2015-05-061-1/+6
| | | | | | | | | | | | | | | Refactoring done on active attribute queries did not take in to account special built-in inputs for the vertex stage. This commit sets them referenced by vertex stage so that they get enumerated properly. Fixes Piglit test 'get-active-attrib-returns-all-inputs' failure. Signed-off-by: Tapani Pälli <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90243 Acked-by: Jose Fonseca <[email protected]> Tested-by: Dieter Nützel <[email protected]> Reviewed-By: Martin Peres <[email protected]>
* i965/gen6: Enable ARB_viewport_array and AMD_vertex_shader_viewport_indexChris Forbes2015-05-061-8/+8
| | | | | Signed-off-by: Chris Forbes <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/gen6: Upload all the SF viewportsChris Forbes2015-05-062-12/+19
| | | | | Signed-off-by: Chris Forbes <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/gen6: Upload all the clip viewportsChris Forbes2015-05-061-19/+21
| | | | | Signed-off-by: Chris Forbes <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/gen6: setup limits for ARB_viewport_arrayChris Forbes2015-05-062-3/+3
| | | | | Signed-off-by: Chris Forbes <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* st/mesa: fix pipe_query_result result initializerBrian Paul2015-05-051-1/+1
| | | | | | Fixes MSVC build error. Reviewed-by: Ilia Mirkin <[email protected]>
* st/mesa: fix st_NewPerfMonitor() declarationBrian Paul2015-05-051-1/+1
| | | | | | Was missing the context parameter. Fixes MSVC warning. Reviewed-by: Ilia Mirkin <[email protected]>
* glsl: add parens in shader_integer_mix() to silence compiler warningBrian Paul2015-05-051-1/+1
| | | | | | | | Silences gcc warning: builtin_functions.cpp:204:23: warning: suggest parentheses around '&&' within '||' [-Wparentheses] Reviewed-by: Ilia Mirkin <[email protected]>
* st/mesa: also try PIPE_FORMAT_R10G10B10A2_UNORM for GL_RGB10Brian Paul2015-05-051-1/+1
| | | | Reviewed-by: Ilia Mirkin <[email protected]>
* nvc0: all queries use an unsigned 64-bits integer by defaultSamuel Pitoiset2015-05-061-5/+7
| | | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]> Reviewed-by: Martin Peres <[email protected]>
* nvc0: make begin_query return false when all MP counters are usedSamuel Pitoiset2015-05-061-5/+8
| | | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]> Reviewed-by: Martin Peres <[email protected]>
* nvc0: define driver-specific query groupsSamuel Pitoiset2015-05-063-0/+76
| | | | | | | | This patch defines "Driver statistics" and "MP counters" groups, but only the latter will be exposed through GL_AMD_performance_monitor. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Martin Peres <[email protected]>
* st/mesa: implement GL_AMD_performance_monitorChristoph Bumiller2015-05-064-0/+500
| | | | | | | | | | | | | | | | | | | | This is based on the original patch of Christoph Bumiller. v2 (Samuel Pitoiset): - improve Gallium interface for this extension - rewrite some parts of the original code - fix compilation errors and piglit tests v3: - only enable this extension when the underlying driver expose GPU counters - get rid of the ring buffer of queries v4: - add a debug message when the maximum number of counters has been reached Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Martin Peres <[email protected]>
* gallium: make pipe_context::begin_query return a booleanSamuel Pitoiset2015-05-0618-34/+51
| | | | | | | | | GL_AMD_performance_monitor must return an error when a monitoring session cannot be started. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Martin Peres <[email protected]>
* gallium: replace pipe_driver_query_info::max_value by a unionSamuel Pitoiset2015-05-066-27/+36
| | | | | | | | This allows queries to return different numeric types. Signed-off-by: Samuel Pitoiset <samuel.pitoiset at gmail.com> Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Martin Peres <[email protected]>
* gallium: add new numeric types to pipe_query_resultSamuel Pitoiset2015-05-061-0/+8
| | | | | | | | This will be used by GL_AMD_performance_monitor. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Martin Peres <[email protected]>
* gallium: add new fields to pipe_driver_query_infoSamuel Pitoiset2015-05-065-20/+30
| | | | | | | | | | | | | | According to the spec of GL_AMD_performance_monitor, valid type values returned are UNSIGNED_INT, UNSIGNED_INT64_AMD, PERCENTAGE_AMD, FLOAT. This also introduces the new field group_id in order to categorize queries into groups. v2: add PIPE_DRIVER_QUERY_TYPE_BYTES v3: fix incorrect query type for radeon and svga drivers Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Martin Peres <[email protected]>
* gallium: add pipe_screen::get_driver_query_group_infoSamuel Pitoiset2015-05-063-0/+35
| | | | | | | | | | | | | | Driver queries are organized as a single hierarchy where queries are categorized into groups. Each group has a list of queries and a maximum number of queries that can be sampled. The list of available groups can be obtained using pipe_screen::get_driver_query_group_info. This will be used by GL_AMD_performance monitor. v2: add group type (CPU/GPU) Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Martin Peres <[email protected]>
* mesa: fix shininess check for ffvertex_prog v2Tim Rowley2015-05-051-1/+1
| | | | | | | | Switch to using VERT_BIT_GENERIC macro, as varying_vp_inputs is a bitmask. Reviewed-by: Ilia Mirkin <[email protected]> Cc: [email protected]
* i965/aa: fixing anti-aliasing bug for thinnest width lines - GEN7Marius Predut2015-05-051-3/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | On SNB and IVB hw, for 1 pixel line thickness or less, the general anti-aliasing algorithm give up - garbage line is generated. Setting a Line Width of 0.0 specifies the rasterization of the “thinnest” (one-pixel-wide), non-antialiased lines. Lines rendered with zero Line Width are rasterized using Grid Intersection Quantization rules as specified by bspec section 6.3.12.1 Zero-Width (Cosmetic) Line Rasterization. v2: Daniel Stone: Fix = used instead of == in an if-statement. v3: Ian Romanick: Use "._Enabled" flag insteed ".Enabled". Add code comments. re-word wrap the commit message. Add a complete bugzillia list. Improve the hardcoded values to produce better results. v4: Matt Turner: typo fixes and adjust <= 1.49 to become < 1.5 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=28832 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=9951 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=27007 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=60797 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=15006 Acked-by: Chris Forbes <[email protected]> Acked-by: Kenneth Graunke <[email protected]> Signed-off-by: Marius Predut <[email protected]>
* i965: Fix missing type in local variable declaration.Kenneth Graunke2015-05-051-1/+1
| | | | | | | | | Trivial. Fixes the following compiler warning (from GCC 5.1.0): brw_context.c:629:10: warning: type defaults to ‘int’ in declaration of ‘simd_size’ [-Wimplicit-int] Signed-off-by: Kenneth Graunke <[email protected]>
* i965/vec4: Use same type for immediate, for compaction.Matt Turner2015-05-051-1/+1
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* i965/aa: fixing anti-aliasing bug for thinnest width lines - GEN6Marius Predut2015-05-051-3/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | On SNB and IVB hw, for 1 pixel line thickness or less, the general anti-aliasing algorithm give up - garbage line is generated. Setting a Line Width of 0.0 specifies the rasterization of the “thinnest” (one-pixel-wide), non-antialiased lines. Lines rendered with zero Line Width are rasterized using Grid Intersection Quantization rules as specified by bspec section 6.3.12.1 Zero-Width (Cosmetic) Line Rasterization. v2: Daniel Stone: Fix = used instead of == in an if-statement. v3: Ian Romanick: Use "._Enabled" flag insteed ".Enabled". Add code comments. re-word wrap the commit message. Add a complete bugzillia list. Improve the hardcoded values to produce better results. v4: Matt Turner: typo fixes and adjust <= 1.49 to become < 1.5 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=28832 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=9951 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=27007 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=60797 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=15006 Acked-by: Chris Forbes <[email protected]> Acked-by: Kenneth Graunke <[email protected]> Signed-off-by: Marius Predut <[email protected]>
* i965: Remove end-of-thread SEND alignment code.Matt Turner2015-05-051-12/+3
| | | | | | | This was present in Eric's initial implementation of the compaction code for Sandybridge (commit 077d01b6). There is no documentation saying this is necessary, and removing it causes no regressions in piglit on any platform.
* i965: Add XRGB8888 format to intel_screen_make_configsBoyan Ding2015-05-051-1/+2
| | | | | | | | | | | | | | Some application, such as drm backend of weston, uses XRGB8888 config as default. i965 doesn't provide this format, but before commit 65c8965d, the drm platform of EGL takes ARGB8888 as XRGB8888. Now that commit 65c8965d makes EGL recognize format correctly so weston won't start because it can't find XRGB8888. Add XRGB8888 format to i965 just as other drivers do. Cc: [email protected] Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89689 Signed-off-by: Boyan Ding <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]>
* nir: add nir_array.h to the sources listEmil Velikov2015-05-051-0/+1
| | | | | | | Otherwise `make distcheck' will fail. Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* glsl: don't lower fragdata array if the output data types don't matchSamuel Iglesias Gonsalvez2015-05-051-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 7e414b58640aee6e243d337e72cea290c354f632 broke the gl_FragData array into separate gl_FragData[i] variables, so drivers can eliminate useless writes to gl_FragData improving their performance. The problem occurs when GLSL IR code is linked in the following case: * The FS output variable base data type does not match gl_FragData one (float vector) * The FS output variable is replaced by gl_out_FragDataX because of commit 7e414b58640aee6 with X from 0 to GL_MAX_DRAW_BUFFERS. Then the FS output variable base data type is lost in the resulting GLSL IR, making that the driver does a wrong assignment to gl_out_FragData components because of unmatching data types. This patch reverts the fragdata array lowering when the output var base data type doesn't match gl_out_FragData, i.e., when output variable base data type is not a float or a float vector. This patch fixes 250 dEQP tests (tested in an Intel Haswell machine) dEQP-GLES3.functional.fragment_out.random.* (22 failed tests) dEQP-GLES3.functional.fragment_out.array.uint.* (120 failed tests) dEQP-GLES3.functional.fragment_out.array.int.* (108 failed tests) Signed-off-by: Samuel Iglesias Gonsalvez <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965/skl: Align compressed textures to four times the block sizeNeil Roberts2015-05-051-4/+27
| | | | | | | | | | | | On Skylake it is possible to choose your own alignment values for compressed textures but they are expressed as a multiple of the block size. The minimum alignment value we can use is 4 so we effectively have to align to 4 times the block size. This patch makes it initially set mt->align_[wh] to the large alignment value and then later divides it by the block size so that it can be uploaded as part of the surface state. Reviewed-by: Ben Widawsky <[email protected]>
* egl: image_dma_buf_export - use KHR 64-bit typeDave Airlie2015-05-053-3/+3
| | | | | | | | After talking to Jon Leech he suggested this should be fine. update spec to the version in the registry. Signed-off-by: Dave Airlie <[email protected]>
* glapi/es3.1: Add support for GLES versions > 3.0Ian Romanick2015-05-041-2/+2
| | | | | | | | | | | | Make the checks in the Python script and the generated code more generic to support arbitrary GLES versions >= 2.0. The updated dispatch_sanity.cpp test discovered this problem. Without this, the next patch would erroneously enable GLES 3.1 functions in GLES 2.0 and GLES 3.0. Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* glsl/es3.1: Allow misc ARB_gpu_shader5 built-ins in GLSL ES 3.10Ian Romanick2015-05-041-11/+11
| | | | | Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* glsl/es3.1: Allow textureGather and textureGatherOffset in GLSL ES 3.10Ian Romanick2015-05-041-29/+61
| | | | | Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Tapani Pälli <[email protected]>
* glsl/es3.1: Allow enhnaced packing functions in GLSL ES 3.10Ian Romanick2015-05-041-6/+7
| | | | | | Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Tapani Pälli <[email protected]>
* glsl/es3.1: Allow interger mix built-ins in GLSL ES 3.10Ian Romanick2015-05-045-7/+55
| | | | | | | | v2: Add missing lexer support. Noticed by Tapani. Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Tapani Pälli <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]> [v1]
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