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* mesa: remove WGLAPI macroBrian Paul2013-11-041-16/+0
| | | | | | WGLAPI was defined in glheader.h but wasn't used anywhere. Reviewed-by: Matt Turner <[email protected]>
* i965: Expose brw_reg_from_fs_reg() to other files.Kenneth Graunke2013-11-042-1/+3
| | | | | | This will be useful for Broadwell code as well. Signed-off-by: Kenneth Graunke <[email protected]>
* i965: Combine gen6_clip_state.c and gen7_clip_state.c.Kenneth Graunke2013-11-043-140/+42
| | | | | | | | | | The changes between Gen6-7 are minimal, and can easily be solved with an extra generation check. This cuts a lot of duplicated code. It also helps prevent even more duplication for Broadwell. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* dri/nouveau: Fix nouveau_init_screen2 breakage.Francisco Jerez2013-11-041-16/+15
| | | | | | | Fix incorrect init ordering in nouveau_init_screen2 caused by 083f66fdd6451648fe355b64b02b29a6a4389f0d. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=71172
* i965/gen7: Add instruction latency estimates for untyped atomics and reads.Francisco Jerez2013-11-041-0/+39
| | | | | | | | The latency information has been obtained empirically from measurements taken on Haswell and Ivy Bridge. Acked-by: Paul Berry <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965/gen7: Handle atomic instructions from the VEC4 back-end.Francisco Jerez2013-11-042-2/+110
| | | | | | | | | | | | | This can deal with all the 15 32-bit untyped atomic operations the hardware supports, but only INC and PREDEC are going to be exposed through the API for now. v2: Represent atomics as GLSL intrinsics. Add support for variably indexed atomic counter arrays. v3: Add comment on why we don't need to assign uniform storage for atomic counters. Reviewed-by: Paul Berry <[email protected]>
* i965/gen7: Handle atomic instructions from the FS back-end.Francisco Jerez2013-11-042-2/+141
| | | | | | | | | | | | | | This can deal with all the 15 32-bit untyped atomic operations the hardware supports, but only INC and PREDEC are going to be exposed through the API for now. v2: Represent atomics as GLSL intrinsics. Add support for variably indexed atomic counter arrays. Fix interaction with fragment discard. v3: Add comment on why we don't need to assign uniform storage for atomic counters. Reviewed-by: Paul Berry <[email protected]>
* i965: Add a 'has_side_effects' back-end instruction predicate.Francisco Jerez2013-11-045-17/+34
| | | | | | | | | | | | | This patch fixes the three dead code elimination passes and the VEC4/FS instruction scheduling passes so they leave instructions with side effects alone. At some point it might be interesting to have the instruction scheduler calculate the exact memory dependencies between atomic ops, but they're rare enough that it seems unlikely that it will make any practical difference. Reviewed-by: Paul Berry <[email protected]>
* clover: Calculate optimal work group size when it's not specified by the user.Francisco Jerez2013-11-045-15/+176
| | | | | | | | Inspired by a patch sent to the mailing list by Tom Stellard, but using a different algorithm to calculate the optimal block size that has been found to be considerably more effective. Reviewed-by: Tom Stellard <[email protected]>
* clover: Constify some command_queue arguments.Francisco Jerez2013-11-041-4/+4
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* clover: Workaround compiler bug present in GCC 4.7.0-4.7.2.Francisco Jerez2013-11-041-16/+13
| | | | | Variadic template aliases make these versions of GCC very confused, write down the full type spec instead.
* st/xorg: handle updates to DamageUnregister APIEmil Velikov2013-11-041-0/+4
| | | | | | | | | | | | | | xserver 1.14.99.2 simplified the DamageUnregister API, by dropping the drawable argument. Follow xf86-video-intel and xf86-video-vmware approach and handle the new API by checking XORG_VERSION_CURRENT. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=71110 Reported-by: Michał Górny <[email protected]> Reported-by: Vinson Lee <[email protected]> Tested-by: Vinson Lee <[email protected]> Reviewed-by: Brian Paul <[email protected]> Signed-off-by: Emil Velikov <[email protected]>
* mesa: remove Watcom C supportBrian Paul2013-11-043-45/+0
| | | | Reviewed-by: Eric Anholt <[email protected]>
* mesa: remove BUILD_FOR_SNAP bitsBrian Paul2013-11-042-7/+5
| | | | Reviewed-by: Eric Anholt <[email protected]>
* r600g: properly unbind a DSA state being deleted in r600_delete_dsa_stateMarek Olšák2013-11-042-2/+9
| | | | Tested-by: Christian König <[email protected]>
* radeonsi: implement ARB_vertex_type_2_10_10_10_revMarek Olšák2013-11-041-0/+7
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* r600g,radeonsi: properly expose texture buffer formatsMarek Olšák2013-11-043-9/+24
| | | | This exposes GL_ARB_texture_buffer_object_rgb32.
* radeonsi: implement texture buffer objectsMarek Olšák2013-11-043-54/+137
| | | | GLSL 1.40 is done.
* radeonsi: report our border color behaviorMarek Olšák2013-11-041-1/+3
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* radeonsi: bind a dummy constant buffer in place of NULL buffersMarek Olšák2013-11-043-0/+29
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* radeonsi: implement uniform buffer objectsMarek Olšák2013-11-044-31/+41
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* tgsi/scan: set maximum index for each constant bufferMarek Olšák2013-11-042-1/+13
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* radeonsi: try to fix IA_MULTI_VGT_PARAM programmingMarek Olšák2013-11-043-2/+8
| | | | This doesn't make any difference on Bonaire, but it might help on Hawaii.
* winsys/radeon: use type-3 NOPs for CS padding on CIKMarek Olšák2013-11-041-2/+7
| | | | The type-2 NOPs are said to be unstable. It doesn't make a difference here.
* clover: fix build with LLVM 3.4Aaron Watry2013-11-041-5/+0
| | | | | | | | dso_list was added as an argument for createInternalizePass in 3.4, and then it was removed again in the same llvm version. Tested-by: Mike Lothian <[email protected]> Reviewed-by: Tom Stellard <[email protected]>
* draw: move type construction out of loopBrian Paul2013-11-041-1/+3
| | | | | | We can create clip_ptr_type once instead of n times inside the loop. Reviewed-by: Roland Scheidegger <[email protected]>
* i965: Add driconf option clamp_max_samplesChad Versace2013-11-032-12/+67
| | | | | | | | | | | | | | | | | | | | The new option clamps GL_MAX_SAMPLES to a hardware-supported MSAA mode. If negative, then no clamping occurs. v2: (for Paul) - Add option to i965 only, not to all DRI drivers. - Do not realy on int->uint cast to convert negative values to large positive values. Explicitly check for clamp_max_samples < 0. v3: (for Ken) - Don't allow clamp_max_samples to alter context version. - Use clearer for-loop and correct comment. - Rename variables. v4: (for Ken) - Merge identical if-branches. Reviewed-and-tested-by: Kenneth Graunke <[email protected]> Signed-off-by: Chad Versace <[email protected]>
* i965: Fix logic_op check.Vinson Lee2013-11-031-2/+1
| | | | | | | Fixes "Macro compares unsigned to 0" defect reported by Coverity. Signed-off-by: Vinson Lee <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* i915: Fix logic_op check.Vinson Lee2013-11-031-2/+1
| | | | | | | Fixes "Macro compares unsigned to 0" defect reported by Coverity. Signed-off-by: Vinson Lee <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* i965: Initialize vec4_visitor member variables.Vinson Lee2013-11-031-1/+6
| | | | | | | Fixes "Uninitialized pointer field" defect reported by Coverity. Signed-off-by: Vinson Lee <[email protected]> Reviewed-by: Paul Berry <[email protected]>
* gallium/targets: remove vdpau-softpipeMarek Olšák2013-11-022-76/+0
| | | | Reviewed-by: Christian König <[email protected]>
* gallium/targets: remove xvmc-softpipeMarek Olšák2013-11-022-76/+0
| | | | Reviewed-by: Christian König <[email protected]>
* gallium/targets: remove r300/vdpauMarek Olšák2013-11-022-78/+0
| | | | Reviewed-by: Christian König <[email protected]>
* gallium/targets: remove r300/xvmcMarek Olšák2013-11-022-73/+0
| | | | Reviewed-by: Christian König <[email protected]>
* gallium/targets: remove radeonsi/xorgMarek Olšák2013-11-023-220/+0
| | | | Reviewed-by: Christian König <[email protected]>
* gallium/targets: remove r600/xorgMarek Olšák2013-11-023-226/+0
| | | | Reviewed-by: Christian König <[email protected]>
* freedreno/a3xx/texture: min/max lodRob Clark2013-11-011-5/+3
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/a3xx: update envytools headersRob Clark2013-11-014-8/+22
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/a3xx: fix VS out / FS in linkingRob Clark2013-11-013-7/+47
| | | | | | | | Actually link VS out / FS in based on semantic info, keeping in mind that position/pointsize can also be an input to the FS. This fixes a few fragment shaders which were using gl_Position. Signed-off-by: Rob Clark <[email protected]>
* freedreno/a3xx: allow num_samplers != num_texturesRob Clark2013-11-012-56/+55
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/a3xx/compiler: highp frag shaderRob Clark2013-11-014-12/+14
| | | | | | | | | | | | | | Fixes use of full-precision in fragment shader (ie. don't clobber r0.x since that can be used by future bary instructions for varying fetch). And makes use of full-precision the default in fragment shader (but can be overriden via FD_MESA_DEBUG=fraghalf). Seems like half precision is often not enough for texture coordinates. The blob compiler is clever enough to keep texture coords in full precision registers while using half precision for everything else. But we aren't quite that clever yet, so better to default to full precision. Signed-off-by: Rob Clark <[email protected]>
* freedreno/a3xx/compiler: relative addressing fixes.Rob Clark2013-11-011-28/+48
| | | | | | | Handle some relative addressing constraints: cannot handle const or relative in cat5 and src2 of cat3. Signed-off-by: Rob Clark <[email protected]>
* freedreno: we do actually support sqrtRob Clark2013-11-012-0/+8
| | | | Signed-off-by: Rob Clark <[email protected]>
* i965: Enable ARB_sample_shading on intel hardware >= gen6Anuj Phogat2013-11-011-0/+1
| | | | | | Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Paul Berry <[email protected]> Reviewed-by: Ken Graunke <[email protected]>
* i965/gen7: Enable the features required for GL_ARB_sample_shadingAnuj Phogat2013-11-011-5/+56
| | | | | | | | | | | | | | | | | | | | - Enable GEN7_WM_MSDISPMODE_PERSAMPLE, GEN7_WM_POSOFFSET_SAMPLE, GEN7_WM_OMASK_TO_RENDER_TARGET as per extension's specification. - Only enable one of GEN7_WM_8_DISPATCH_ENABLE or GEN7_WM_16_DISPATCH_ENABLE when GEN7_WM_MSDISPMODE_PERSAMPLE is enabled. Refer IVB PRM Vol. 2, Part 1, Page 288 for details. V2: - Use shared function _mesa_get_min_invocations_per_fragment(). - Use brw_wm_prog_data variables: uses_pos_offset, uses_omask. V3: - Enable simd16 dispatch with per sample shading. - Make changes to give preference to 'simd16 only' mode over 'simd8 only' mode in case of non 1x per sample shading. Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Paul Berry <[email protected]>
* i965/gen6: Enable the features required for GL_ARB_sample_shadingAnuj Phogat2013-11-011-5/+56
| | | | | | | | | | | | | | | | | | | | - Enable GEN6_WM_MSDISPMODE_PERSAMPLE, GEN6_WM_POSOFFSET_SAMPLE, GEN6_WM_OMASK_TO_RENDER_TARGET as per extension's specification. - Only enable one of GEN6_WM_8_DISPATCH_ENABLE or GEN6_WM_16_DISPATCH_ENABLE when GEN6_WM_MSDISPMODE_PERSAMPLE is enabled. Refer SNB PRM Vol. 2, Part 1, Page 279 for details. V2: - Use shared function _mesa_get_min_invocations_per_fragment(). - Use brw_wm_prog_data variables: uses_pos_offset, uses_omask. V3: - Enable simd16 dispatch with per sample shading. - Make changes to give preference to 'simd16 only' mode over 'simd8 only' mode in case of non 1x per sample shading. Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Paul Berry <[email protected]>
* i965: Add FS backend for builtin gl_SampleMask[]Anuj Phogat2013-11-015-0/+61
| | | | | | | | | | | | | | V2: - Update comments - Add a special backend instructions to compute sample_mask. - Add a new variable uses_omask in brw_wm_prog_data. V3: - Make changes to support simd16 mode. - Delete redundant AND instruction and handle the register stride in FS backend instruction. Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Paul Berry <[email protected]>
* i965: Add FS backend for builtin gl_SampleIDAnuj Phogat2013-11-017-0/+94
| | | | | | | | | | | | | V2: - Update comments - Add compute_sample_id variables in brw_wm_prog_key - Add a special backend instruction to compute sample_id. V3: - Make changes to support simd16 mode. Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Paul Berry <[email protected]>
* i965: Add FS backend for builtin gl_SamplePositionAnuj Phogat2013-11-016-0/+95
| | | | | | | | | | | | | V2: - Update comments. - Add compute_pos_offset variable in brw_wm_prog_key. - Add variable uses_pos_offset in brw_wm_prog_data. V3: - Make changes to support simd16 mode. Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Paul Berry <[email protected]>
* i965: Don't do vector splitting for ir_var_system_valueAnuj Phogat2013-11-011-0/+1
| | | | | | | | | | | | | This is required while adding builtin system value vec{2, 3, 4} variables. For example: (declare (sys) vec2 gl_SamplePosition) Without this patch above glsl ir splits in to: (declare (temporary) float gl_SamplePosition_x) (declare (temporary) float gl_SamplePosition_y) Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
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