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* Merge tag 'mesa_7_4_rc1' into debian-experimentalJulien Cristau2009-03-23129-2850/+3427
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| * mesa: prep for 7.4-rc1 releaseBrian Paul2009-03-201-1/+1
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| * r300: don't crash on sw tcl hw if point size vertex attrib is sentBrian Paul2009-03-201-2/+2
| | | | | | | | (cherry picked from master, commit 005ad1a71d8de318a69ba18d896677d89602e0db)
| * mesa: avoid setting texObj->_Complete = GL_FALSE when there's no state changeBrian Paul2009-03-181-31/+37
| | | | | | | | | | | | | | | | Avoid a little bit of unneeded state validation and fixes a bug where the texture complete flags was set to false, but we didn't signal _NEW_TEXTURE. Fixes piglit tex1d-2dborder failure. (cherry picked from commit aad3f546a046fe40b771e5d5f965b29189821d51)
| * mesa: add no-change testing for a few more texture parametersBrian Paul2009-03-181-9/+21
| | | | | | | | (cherry picked from commit 37c768b36aad22ecad48c7caab272354383e26a7)
| * i965: fix polygon stipple when rendering to FBORobert Ellison2009-03-182-7/+34
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The polygon stipple pattern, like the viewport and the polygon face orientation, must be inverted on the i965 when rendering to a FBO (which itself has an inverted pixel coordinate system compared to raw Mesa). In addition, the polygon stipple offset, which orients the stipple to the window system, disappears when rendering to an FBO (because the window system offset doesn't apply, and there's no associated FBO offset). With these fixes, the conform triangle and polygon stipple tests pass when rendering to texture. (cherry picked from commit 29309b45b011b4c44721b8f7346272fb22a4d4c2)
| * i965: fix polygon face orientation when rendering to FBORobert Ellison2009-03-182-4/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In the i965, the FBO coordinate system is inverted from the standard OpenGL/Mesa coordinate system; that means that the viewport and the polygon face orientation have to be inverted if rendering to a FBO. The viewport was already being handled correctly; but polygon face was not. This caused a conform failure when rendering to texture with two-sided lighting enabled. This fixes the problem in the i965 driver, and adds to the comment about the gl_framebuffer "Name" field so that this isn't a surprise to other driver writers. (cherry picked from commit 6dceeb2eb804d708639d68a13a924d65f366458a)
| * swrast: use better _swrast_compute_lambda() functionBrian Paul2009-03-171-6/+6
| | | | | | | | | | | | | | | | | | | | | | | | The MAX-based function can produce values that are non-monotonic for a span which causes glitches in texture filtering. The sqrt-based one avoids that. This is perhaps slightly slower than before, but the difference probably isn't noticable given we're doing software mipmap filtering. Issue reported by Nir Radian <[email protected]> (cherry picked from master, commit c334ce273e946733928339b1c7f9a02ccdef1b4b)
| * Mark current bits as 2009Q1-RC1 for Intel driver.intel_2009q1_rc1Ian Romanick2009-03-161-1/+1
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| * i965: init dest reg CondMask = COND_TR (the proper default)Brian Paul2009-03-131-3/+2
| | | | | | | | | | Plus fix up a debug printf. (cherry picked from commit 20f49252e1fe2e72bb620c26292f33d5315452a1)
| * glsl: fix vec4_texp_rect IR code (need projective version) (cherry picked ↵Brian Paul2009-03-131-1/+1
| | | | | | | | from commit ad2cfa41992d0676881440596c43ab6021c1b025)
| * i965: check if we run out of GRF/temp registersBrian Paul2009-03-131-2/+26
| | | | | | | | | | | | | | | | Before this change we would up emitting instructions with invalid register numbers. This typically (but not always) hung the GPU. For now, just prevent emitting bad instructions to avoid hangs. Still need to do some kind of proper error recovery. (cherry picked from commit e60b3067d81319236d63ad497e70658fd2e14eb3)
| * mesa: added _mesa_fprintf() wrapper (cherry picked from commit ↵Brian Paul2009-03-132-1/+17
| | | | | | | | 596b8fbbbf65cef227ce60216a57d4bbfd627099)
| * i965: fix emit_math1() function used for scalar instructionsBrian Paul2009-03-131-9/+32
| | | | | | | | | | | | | | | | | | | | Instructions such as RCP, RSQ, LOG must smear the result of the function across the dest register's X, Y, Z and W channels (subject to write masking). Before this change, only the X component was getting written. Among other things, this fixes cube map texture sampling in GLSL shaders (since cube lookups involve normalizing the texcoord). (cherry picked from commit 348580197802406fc36219dc3f1ab90fbb8f4717)
| * i965: rewrite the code for handling shader subroutine callsBrian Paul2009-03-136-64/+187
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Previously, the prog_instruction::Data field was used to map original Mesa instructions to brw instructions in order to resolve subroutine calls. This was a rather tangled mess. Plus it's an obstacle to implementing dynamic allocation/growing of the instruction buffer (it's still a fixed size). Mesa's GLSL compiler emits a label for each subroutine and CAL instruction. Now we use those labels to patch the subroutine calls after code generation has been done. We just keep a list of all CAL instructions that needs patching and a list of all subroutine labels. It's a simple matter to resolve them. This also consolidates some redundant post-emit code between brw_vs_emit.c and brw_wm_glsl.c and removes some loops that cleared the prog_instruction::Data fields at the end. Plus, a bunch of new comments. (cherry picked from commit c51c822ee02cb47ddba46da668577d51b7c02831)
| * intel: Fix bpp setting of blits to 8bpp targets.Eric Anholt2009-03-131-0/+2
| | | | | | | | | | | | This was causing hangs in cairogears, as we would blit to the 8bpp target (A8 texture) as 16bpp, and stomp over state objects. (cherry picked from commit 19e134051c1025bbfe3838108492d705ab2b5b8b)
| * i965: add software fallback for conformant 3D textures and GL_CLAMPRobert Ellison2009-03-134-10/+40
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The i965 hardware cannot do GL_CLAMP behavior on textures; an earlier commit forced a software fallback if strict conformance was required (i.e. the INTEL_STRICT_CONFORMANCE environment variable was set) and 2D textures were used, but it was somewhat flawed - it could trigger the software fallback even if 2D textures weren't enabled, as long as one texture unit was enabled. This fixes that, and adds software fallback for GL_CLAMP behavior with 1D and 3D textures. It also adds support for a particular setting of the INTEL_STRICT_CONFORMANCE environment variable, which forces software fallbacks to be taken *all* the time. This is helpful with debugging. The value is: export INTEL_STRICT_CONFORMANCE=2 (cherry picked from commit 34683150878e0af0859c94d0c1f0c4bf8395b042)
| * mesa: don't draw arrays if vertex position array is not enabledBrian Paul2009-03-131-3/+12
| | | | | | | | | | | | | | | | | | For regular GL, we must have vertex positions in order to draw. But ES2 doesn't have that requirement (positions can be computed from any array of data). See bug 19911. (cherry picked from commit 97dd2ddbd97ba95e8bc8ab572ec05e8081556e1e)
| * i965: texture fixes: bordered textures, fallback renderingRobert Ellison2009-03-131-3/+31
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | i965 doesn't natively support GL_CLAMP; it treats it like GL_CLAMP_TO_EDGE, which fails conformance tests. This fix adds a clause to the check_fallbacks() test to check whether GL_CLAMP is in use on any enabled 2D texture. If so, and if strict conformance is required (via INTEL_STRICT_CONFORMANCE), a software fallback is mandated. In addition, validate textures *before* checking for fallbacks, rather than after; otherwise, the texture state is never validated and can't be trusted. (In particular, if texturing is enabled and the sampler would access any level beyond level 0 of a texture, the sampler will segfault, because texture validation sets the firstLevel and lastLevel fields of a texture object so that the valid levels will be mapped and accessed correctly. If texture validation doesn't occur, only level 0 is accessed correctly, and that only because firstLevel and lastLevel happen to be set to 0.) (cherry picked from commit 17c7852bf93c4d4edf0c2cf0bdc553d399e2f51a)
| * texmem: fix typo from brianp's changes.Dave Airlie2009-03-131-1/+1
| | | | | | | | | | Reported by cjb via tinderbox on irc (cherry picked from commit 487a55af7864a3b16531af5481aab7f585622e4a)
| * mesa: use an array for current texture objectsBrian Paul2009-03-1315-264/+168
| | | | | | | | | | Use loops to consolidate lots of texture object code. (cherry picked from commit 9818734e0148510967ca9ee0d1aa8b196b509f02)
| * mesa: use an array for default texture objectsBrian Paul2009-03-134-90/+72
| | | | | | | | | | | | Replace Default1D/2D/3D/Cube/etc with DefaultTex[TEXTURE_x_INDEX]. The same should be done with the Current1D/2D/3D/etc pointers... (cherry picked from commit 4d24b639d160fe485a3e8f7395e7654538be29e0)
| * Fix an i965 assertion failure on glClear()Robert Ellison2009-03-131-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | While running conform with render-to-texture: conform -d 33 -v 2 -t -direct the i965 driver failed this assertion: intel_clear.c:77: intel_clear_tris: Assertion `(mask & ~((1 << BUFFER_BACK_LEFT) | (1 << BUFFER_FRONT_LEFT) | (1 << BUFFER_DEPTH) | (1 << BUFFER_STENCIL))) == 0' failed. The problem is that intel_clear_tris() is called by intelClear() to clear any and all of the available color buffers, but intel_clear_tris() actually only handles the back left and front left color buffers; so the assertion fails as soon as you try to clear a non-standard color buffer. The fix is to have intelClear() only call intel_clear_tris() with buffers that intel_clear_tris() can support. intelClear() already backs down to _swrast_Clear() for all buffers that aren't handled explicitly. (cherry picked from commit 0ccbc3c905f0594a35d72887a1f115e148aaa596)
| * intel: fix datatype typo, s/GLboolean/GLuint/Brian Paul2009-03-131-1/+1
| | | | | | | | | | Fixes mysterious failures in glean glsl1 test. (cherry picked from commit da2b661ee45a2754bab06359477428ef7df570ca)
| * intel: Fix intelSetTexBuffer miptree leak.Kristian Høgsberg2009-03-131-2/+7
| | | | | | | | | | The intelImage also holds a reference to the miptree, so unref that as well. (cherry picked from commit 5b354d39d466e3a463c6766fe06f737aa6e6b7bd)
| * intel: tell libdrm whether we want a cpu-ready or gpu-ready BO for regions.Eric Anholt2009-03-137-13/+27
| | | | | | | | | | | | | | | | | | | | | | This lets us avoid allocing new buffers for renderbuffers, finalized miptrees, and PBO-uploaded textures when there's an unreferenced but still active one cached, while also avoiding CPU waits for batchbuffers and CPU-uploaded textures. The size of BOs allocated for a desktop running current GL cairogears on i915 is cut in half with this. Note that this means we require libdrm 2.4.5. (cherry picked from commit 40dd024be618d805b3744e15d25e115018641324)
| * i965: Fix render target read domains.Eric Anholt2009-03-131-2/+1
| | | | | | | | | | | | | | | | | | | | | | | | We were asking for something illegal (write_domain != 0 && read_domains != write_domain) because at the time of writing the region surfaces were used for texturing occasionally as well, and we weren't really clear on the model GEM was going to use. This reliably triggered a kernel bug with domain handling, resulting in oglconform mustpass.c failure. Of course, it only became visible after 01bc4d441fd6821ad9fc20d5e9544e4e587e4ff0 cleaned up some gratuitous flushing. (cherry picked from commit 078e8a61b2aa547c6794f586a5c8bfaa575bb066)
| * intel: Don't do the extra MI_FLUSH in flushing except when doing glFlush().Eric Anholt2009-03-131-5/+17
| | | | | | | | | | | | Everything other than "make sure the last rendering ends up visible on the screen" doesn't need that behavior. (cherry picked from commit 01bc4d441fd6821ad9fc20d5e9544e4e587e4ff0)
| * intel: don't crash when dri2 tells us about buffers we don't care about. ↵Eric Anholt2009-03-131-0/+3
| | | | | | | | (cherry picked from commit f82f1ffba9f2e5971a6a3f3927ae3b22b798bab2)
| * dri2: Initialize variables for the getbuffers round-trip reduction.Eric Anholt2009-03-131-0/+2
| | | | | | | | | | Missed setting the initial values which usually didn't hurt at runtime. (cherry picked from commit 680c708deeb4d18474cf7ba86c587dede51d3633)
| * intel: Fix tri clear to do FBO color attachments as well.Eric Anholt2009-03-131-8/+25
| | | | | | | | | | | | This is a 2% win in fbo_firecube, and would avoid a sw fallback for masked clears. (cherry picked from commit fd51cf1531f1630ee1cb154b3b7fefad9ed820f1)
| * i965: Fix fallback on stencil drawing to fbo when the visual lacks stencil.Eric Anholt2009-03-131-2/+2
| | | | | | | | | | Noticed this with the fbotexture demo. (cherry picked from commit c06f4e2a371a917cfcce47e7ee4aa8f1f6528e3b)
| * i965: need to disable current shader, if any, in intel_clear_tris()Brian Paul2009-03-131-0/+9
| | | | | | | | | | Fixes bad background in all the progs/glsl/ tests. (cherry picked from commit 60b3fe6c19eb881f6193ba46450c0c9f559a10e5)
| * intel: Speed up glDrawPixels(GL_ALPHA) by using an alpha texture format. ↵Eric Anholt2009-03-131-5/+6
| | | | | | | | (cherry picked from commit 0b63f6449e095fa3b5ef510e1c1eadc2e0e0ea36)
| * intel: Fix some state leakage of {Client,}ActiveTexture in metaops.Eric Anholt2009-03-132-0/+10
| | | | | | | | | | Found while debugging cairo-gl. (cherry picked from commit d11981e0d722282894b5012d37b2960ee3fbfac2)
| * i965: Remove brw->attribs now that we can just always look in the GLcontext. ↵Eric Anholt2009-03-1319-182/+157
| | | | | | | | (cherry picked from commit 052c1d66a1ab1f2665870dc77dab28d20416cdf1)
| * i965: Delete old metaops code now that there are no remaining consumers. ↵Eric Anholt2009-03-1314-684/+25
| | | | | | | | (cherry picked from commit 14321fcfde9e30d0b9f15aab3c9a057271ae6295)
| * i965: init array->Format fields (see bug 19708) (cherry picked from commit ↵Brian Paul2009-03-131-0/+2
| | | | | | | | 628b52241b13132e2d4065b653befdf81236e651)
| * intel: If we're doing a depth clear with tris, do color with it.Eric Anholt2009-03-132-3/+11
| | | | | | | | | | This is a 10% win on the ever-important glxgears not-a-benchmark. (cherry picked from commit 67ee22c89f42146e7befb2fdd39bdd68a5258c30)
| * i915: Only call CalcViewport from DrawBuffers instead of Viewport.Eric Anholt2009-03-133-8/+10
| | | | | | | | | | | | This saves an inadvertent round-trip to the X Server on DrawBuffers, which was hurting some metaops. (cherry picked from commit ac0dfbdf0f5e5dea08ec717ae8c4e1e141b15c05)
| * intel: move some driver functions aroundBrian Paul2009-03-134-82/+95
| | | | | | | | | | A step toward consolidating i915/intel_state.c and i965/intel_state.c (cherry picked from commit 84c8b5bbf980deea6322009354c3331dc5d5eb57)
| * intel: replace custom metaops clear with generic.Eric Anholt2009-03-132-71/+176
| | | | | | | | | | | | No real-world impact on performance seen. Even glxgears seems to be, if anything, happier. (cherry picked from commit c96bac0950eda6e707455b0c1ee29c1d87daf727)
| * intel: make intelUpdateScreenFromSAREA() static (cherry picked from commit ↵Brian Paul2009-03-132-5/+1
| | | | | | | | aae2729aeb3f6eed26e8f7673f47f2b978786bb1)
| * intel: remove unused var (cherry picked from commit ↵Brian Paul2009-03-131-2/+0
| | | | | | | | 66c7f06413cc96a75befa4323677b26a2917ebb3)
| * i915: Add support for a new G33-like chipset.Shaohua Li2009-03-132-2/+13
| | | | | | | | | | | | Signed-off-by: Shaohua Li <[email protected]> Signed-off-by: Eric Anholt <[email protected]> (cherry picked from commit 40290745ea645b52d30f866abfe25ac5d58a755c)
| * i965: fix for RHW workaroundXiang, Haihao2009-03-132-43/+99
| | | | | | | | | | | | | | It is possible that an object whose vertices all are outside of a view plane is passed to clip thread due to the RHW workaround. This object should be rejected by clip thread. Fix bug #19879 (cherry picked from commit 68915fd6fac44dd000080298e3afb0669e8754aa)
| * i965: tell GLSL compiler to emit code using condition codesBrian Paul2009-03-131-0/+3
| | | | | | | | | | | | | | The default for EmitCondCodes got flipped when gallium-0.2 was merged. This fixes GLSL if/else/endif regressions. Drivers that use GLSL should always explicitly set the flag to be safe. (cherry picked from commit a9e753c84cc5acc2a89686a5e4109f3b056d4fb4)
| * tdfx: Fix begin/endquery for current API. (cherry picked from commit ↵Eric Anholt2009-03-131-4/+4
| | | | | | | | 0cb295584ff2e3d442029fe9e079f69fafaf8dd9)
| * i965: add missing break for OPCODE_RET caseBrian Paul2009-03-131-0/+1
| | | | | | | | | | This doesn't effect correctness, but we were emitting an extraneous ADD. (cherry picked from commit 74b6d55864b9264323a09856781f655e453b182b)
| * mesa: more info in error messages (cherry picked from commit ↵Brian Paul2009-03-131-2/+3
| | | | | | | | 1ca05a066b8d8cb8a99da88743a48f7d97f695fe)
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