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* util: Optimize util_is_power_of_two_nonzeroIan Romanick2018-03-291-0/+17
| | | | | | Signed-off-by: Ian Romanick <[email protected]> Suggested-by: Matt Turner <[email protected]> Reviewed-by: Eduardo Lima Mitev <[email protected]>
* util: Use util_is_power_of_two_nonzero in u_vectorIan Romanick2018-03-291-2/+2
| | | | | | | | Previously size=0, element_size=0 would have been allowed. That combination can only lead to despair. Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Alejandro Piñeiro <[email protected]>
* util: Add and use util_is_power_of_two_nonzeroIan Romanick2018-03-295-13/+19
| | | | | Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Eduardo Lima Mitev <[email protected]>
* util: Move util_is_power_of_two to bitscan.h and rename to ↵Ian Romanick2018-03-2937-73/+79
| | | | | | | | | | | util_is_power_of_two_or_zero The new name make the zero-input behavior more obvious. The next patch adds a new function with different zero-input behavior. Signed-off-by: Ian Romanick <[email protected]> Suggested-by: Matt Turner <[email protected]> Reviewed-by: Alejandro Piñeiro <[email protected]>
* meson: use dep_libdrm version for pkg-configDylan Baker2018-03-292-2/+2
| | | | | | | | | This corrects pkg-config to use the libdrm version (as computed by the previous patch) instead of using a hardcoded value that may or may not (probably not) be right. Signed-off-by: Dylan Baker <[email protected]> Reviewed-by: Eric Engestrom <[email protected]>
* glapi: add glBlendBarrier(), glPrimitiveBoundingBox() prototypesBrian Paul2018-03-291-0/+2
| | | | | | | | in glapi_dispatch.c, as we have for many other GLES functions. Fixes a cross-compile issue (missing prototype) when GLES support is disabled. Reviewed-by: Sinclair Yeh <[email protected]>
* st/mesa: silence unhandled switch case warningBrian Paul2018-03-291-1/+2
| | | | | | And improve the unreachable() error message. Reviewed-by: Mathias Fröhlich <[email protected]>
* mesa: Inherit texture view multi-sample information from the original ↵Henri Verbeet2018-03-293-14/+26
| | | | | | | | | | | | | | texture images. Found running "The Witness" in Wine. Without this patch, texture views created on multi-sample textures would have a GL_TEXTURE_SAMPLES of 0. All things considered such views actually work surprisingly well, but when combined with (plain) multi-sample textures in a framebuffer object, the resulting FBO is incomplete because the sample counts don't match. CC: <[email protected]> Signed-off-by: Henri Verbeet <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* radv: fix scanning output_usage_mask with structsSamuel Pitoiset2018-03-291-4/+52
| | | | | | | | | | | | To fix a regression in: dEQP-VK.spirv_assembly.instruction.graphics.variable_init.output.struct And the following regressions (Polaris only): dEQP-VK.glsl.indexing.varying_array.* Fixes: f3275ca01c ("ac/nir: only enable used channels when exporting parameters") Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* nvc0/ir: fix emiting NOTs with predicatesKarol Herbst2018-03-291-0/+2
| | | | | Signed-off-by: Karol Herbst <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* broadcom/vc4: Fix out-of-tree build with automake.Aaron Watry2018-03-281-0/+2
| | | | | Signed-off-by: Aaron Watry <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* broadcom/vc5: Start using nir_opt_move_load_ubo().Eric Anholt2018-03-281-0/+2
| | | | | | In the absence of a general NIR or VIR-level scheduler, this at least avoids spilling in GTF-GLES3.gtf.GL3Tests.uniform_buffer_object.uniform_buffer_object_storage_layouts
* broadcom/vc5: Fix setup of integer surface clear values.Eric Anholt2018-03-281-8/+8
| | | | | | | | I'm disappointed that the compiler didn't warn me about use of uninitialized uc in these paths. Just use the incoming clear color instead of the packing temporary if we're doing our own packing. Fixes GTF-GLES3.gtf.GL3Tests.color_buffer_float.color_buffer_float_clamp_*
* broadcom/vc5: Stop trying to swizzle around RGBA4 clear color.Eric Anholt2018-03-281-12/+2
| | | | | | | | We always want A in the A slot in the tile buffer, and any other swapping should happen elsewhere. Fixes RGBA4-using cases in fbo-clear-formats and GTF-GLES3.gtf.GL3Tests.color_buffer_float.color_buffer_float_clamp_fixed.
* broadcom/vc5: Work around scissor w/h==0 bug same as rasterizer discard.Eric Anholt2018-03-281-2/+15
| | | | | The 7268 HW apparently lets some rendering through in this case. Fixes GTF-GLES2.gtf.GL2FixedTests.scissor.scissor
* st: Don't try to finalize the texture in st_render_texture().Eric Anholt2018-03-281-4/+0
| | | | | | | | | | | | | | | We can't necessarily finalize the texture at this point if we're rendering to a texture image whose format is different from the baselevel's format. This was introduced as a fix for fbo-incomplete-texture-03 in de414f491526610bb260c73805c81ba413388e20, but the later fix for vmware on that testcase in 95d5c48f68b598cfa6db25f44aac52b3e11403cc made it unnecessary. Fixes assertion failures in util_resource_copy_region() in KHR-GLES3.copy_tex_image_conversions.forbidden.* when trying to finalize an R8 texture image to the RG8 texture object's pt. Reviewed-by: Brian Paul <[email protected]>
* drirc: whitelist glthread for Medieval II: TW, Carnivores: DHR, Far Cry 2Marek Olšák2018-03-281-0/+15
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* radv: enable VK_AMD_shader_trinary_minmax extensionDaniel Schürmann2018-03-292-0/+2
| | | | | Reviewed-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]>
* ac: add support for trinary_minmax instructionsDaniel Schürmann2018-03-291-0/+54
| | | | | | | v2: Add missing break (Bas) Reviewed-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]>
* spirv: add support for SPV_AMD_shader_trinary_minmaxDave Airlie2018-03-294-0/+58
| | | | | | | Co-authored-by: Daniel Schürmann <[email protected]> Signed-off-by: Dave Airlie <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]>
* nir: add support for min/max/median of 3 srcsDave Airlie2018-03-291-0/+14
| | | | | | | | | | | These are needed for SPV_AMD_shader_trinary_minmax, the AMD HW supports these. Co-authored-by: Daniel Schürmann <[email protected]> Signed-off-by: Dave Airlie <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]>
* radeonsi: simplify DCC format categoriesMarek Olšák2018-03-281-20/+9
| | | | Reviewed-by: Samuel Pitoiset <[email protected]>
* radeonsi: don't use the SPI barrier management bug workaroundMarek Olšák2018-03-281-0/+5
| | | | Reviewed-by: Samuel Pitoiset <[email protected]>
* radeonsi: use maximum OFFCHIP_BUFFERING on Vega12Marek Olšák2018-03-281-1/+8
| | | | Reviewed-by: Samuel Pitoiset <[email protected]>
* ac/nir: Add workaround for GFX9 buffer views.Bas Nieuwenhuizen2018-03-295-7/+70
| | | | | | | | | | | | | | | | | | | | | On GFX9 whether the buffer size is interpreted as elements or bytes depends on whether IDXEN is enabled in the instruction. If the index is a constant zero, LLVM optimizes IDXEN to 0. Now the size in elements is interpreted in bytes which of course results in out of bounds accesses. The correct fix is most likely to disable the LLVM optimization, but we need something to work with LLVM <= 6.0. radeonsi does the max between stride and element count on the CPU but that results in the size intrinsics returning the wrong size for the buffer. This would cause CTS errors for radv. v2: Also include the store changes. Fixes: e38685cc62e 'Revert "radv: disable support for VEGA for now."' Reviewed-by: Samuel Pitoiset <[email protected]>
* ac/surface: set AddrSurfInfoIn.format = ADDR_FMT_8 for stencil, add assertionsMarek Olšák2018-03-281-0/+8
| | | | | | | Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105738 Tested-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: enable VK_EXT_sampler_filter_minmaxSamuel Pitoiset2018-03-281-0/+1
| | | | | | | Only enable for CIK+ because it's buggy on SI. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: add support for VK_EXT_sampler_filter_minmaxSamuel Pitoiset2018-03-282-1/+70
| | | | | | | The driver only supports the required formats for now. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: rename VEGA10 device nameSamuel Pitoiset2018-03-281-1/+1
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: add support for Vega12Samuel Pitoiset2018-03-283-1/+6
| | | | | | | Based on RadeonSI. Untested. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* autotools: Include intel/dev/meson.build in tarballDylan Baker2018-03-281-0/+1
| | | | | | | Fixes: 272bef0601a1bdb5292771aefc8d62fcbdf4c47f ("intel: Split gen_device_info out into libintel_dev") Signed-off-by: Dylan Baker <[email protected]> Reviewed-by: Eric Engestrom <[email protected]>
* radeonsi: add support for Vega12Marek Olšák2018-03-287-8/+35
| | | | Reviewed-by: Alex Deucher <[email protected]>
* amd/addrlib: update to the latest version for Vega12Marek Olšák2018-03-2817-148/+439
| | | | Reviewed-by: Alex Deucher <[email protected]>
* gbm: remove never-implemented functionEric Engestrom2018-03-282-3/+0
| | | | | | | | | | I assume this was implemented in a previous version of that commit, but was removed in the version that actually landed. Fixes: 8430af5ebe1ee8119e14 "Add support for swrast to the DRM EGL platform" Cc: Giovanni Campagna <[email protected]> Signed-off-by: Eric Engestrom <[email protected]> Reviewed-by: Emil Velikov <[email protected]>
* android: Use new nir intrinsics python scriptsStefan Schake2018-03-281-0/+9
| | | | | | | Fixes: 76dfed8ae2d5 ("nir: mako all the intrinsics") Signed-off-by: Stefan Schake <[email protected]> Acked-by: Rob Clark <[email protected]> Reviewed-by: Tapani Pälli <[email protected]>
* broadcom/vc5: Fix padding of NPOT miplevels >= 2.Eric Anholt2018-03-271-3/+8
| | | | | | | The power-of-two padded size that gets minified is based on level 1's dimensions, not level 0's, which starts to differ at a width of 9. Fixes all failures on texelFetch fs sampler2D 1x1x1-64x64x1
* ac/radeonsi: pass bindless bool to load_sampler_desc()Timothy Arceri2018-03-284-5/+14
| | | | | | | | We also fix the base_index for bindless by using the driver location. Reviewed-by: Samuel Pitoiset <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* st/glsl_to_nir: set driver location for bindless images and samplersTimothy Arceri2018-03-281-1/+2
| | | | Reviewed-by: Marek Olšák <[email protected]>
* radeonsi/nir: set uses_bindless_samplers for samplersTimothy Arceri2018-03-281-0/+3
| | | | | Reviewed-by: Samuel Pitoiset <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* nir: add bindless to nir dataTimothy Arceri2018-03-282-0/+7
| | | | | | Reviewed-by: Iago Toral Quiroga <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]>
* i965: Drop unnecessary bo->align field.Kenneth Graunke2018-03-273-10/+0
| | | | | | | | bo->align is always 0; there's no need to waste 8 bytes storing it. Thanks to C99 initializers zeroing fields, we can completely drop the only read of the field altogether. Reviewed-by: Jason Ekstrand <[email protected]>
* i965: Drop unused alignment parameter from brw_bo_alloc().Kenneth Graunke2018-03-2714-26/+25
| | | | | | brw_bo_alloc no longer uses this parameter, so there's no point. Reviewed-by: Jason Ekstrand <[email protected]>
* i965: Drop alignment parameter from bo_alloc_internal().Kenneth Graunke2018-03-271-7/+6
| | | | | | | | | | | Buffers are always page aligned on 965+ hardware; I believe this extra parameter is a vestige from the Gen2-3 era. All callers pass 0, and in fact we assert that the alignment is 0 unless BO_ALLOC_BUSY is set (for some reason). We can just drop the parameter and set the value to 0 explicitly. Reviewed-by: Jason Ekstrand <[email protected]>
* i965: Drop BO_ALLOC_BUSY in intel_miptree_create_for_bo().Kenneth Graunke2018-03-271-2/+2
| | | | | | | intel_miptree_create_for_bo does not actually allocate a BO, so specifying allocation flags accomplishes nothing and is confusing. Reviewed-by: Jason Ekstrand <[email protected]>
* i965: Drop PIPE_CONTROL_NO_WRITE from various calls.Kenneth Graunke2018-03-274-11/+4
| | | | | | | This is just zero - passing nothing already gives us a post-sync operation of "nothing". Reviewed-by: Lionel Landwerlin <[email protected]>
* nir/intrinsics: Don't report negative dest_componentsJason Ekstrand2018-03-271-1/+1
| | | | | | | | I have no idea why but having dest_components == -1 was causing a memory leak somewhere. Without this, you can't get through a full shader-db run without running out of memory. Reviewed-by: Rob Clark <[email protected]>
* intel/fs: Don't emit a des copy for image ops with has_dest == falseJason Ekstrand2018-03-271-3/+6
| | | | | | | | | | This was causing us to walk dest_components times over a thing with no destination. This happened to work because all of the image intrinsics without a destination also happened to have dest_components == 0. We shouldn't be reading dest_components if has_dest == false. Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* nvc0/ir: fix INTERP_* with indirect inputsIlia Mirkin2018-03-271-3/+4
| | | | | | | | | | | | There were two problems, both of which are fixed now: - The indirect address was not being shifted by 4 - The indirect address was being placed as an argument in the offset case This fixes some of the new interpolateAt* piglits which now test for these situations. Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Karol Herbst <[email protected]>
* nir: fix crash in loop unroll corner caseTimothy Arceri2018-03-281-5/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When an if nesting inside anouther if is optimised away we can end up with a loop terminator and following block that looks like this: if ssa_596 { block block_5: /* preds: block_4 */ vec1 32 ssa_601 = load_const (0xffffffff /* -nan */) break /* succs: block_8 */ } else { block block_6: /* preds: block_4 */ /* succs: block_7 */ } block block_7: /* preds: block_6 */ vec1 32 ssa_602 = phi block_6: ssa_552 vec1 32 ssa_603 = phi block_6: ssa_553 vec1 32 ssa_604 = iadd ssa_551, ssa_66 The problem is the phis. Loop unrolling expects the last block in the loop to be empty once we splice the instructions in the last block into the continue branch. The problem is we cant move phis so here we lower the phis to regs when preparing the loop for unrolling. As it could be possible to have multiple additional blocks/ifs following the terminator we just convert all phis at the top level of the loop body for simplicity. We also add some comments to loop_prepare_for_unroll() while we are here. Fixes: 51daccb289eb "nir: add a loop unrolling pass" Reviewed-by: Jason Ekstrand <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105670
* st/glsl_to_nir: correctly handle arrays packed across multiple varsTimothy Arceri2018-03-281-1/+23
| | | | | | | Fixes piglit test: tests/spec/arb_enhanced_layouts/execution/component-layout/vs-fs-array-interleave-range.shader_test Reviewed-by: Marek Olšák <[email protected]>
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