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* intel/tools/error: Fix null termination of ring name string.Kenneth Graunke2017-11-131-0/+1
| | | | | | Ported from intel_error_decode. We don't want to run off the end. Reviewed-by: Chris Wilson <[email protected]>
* intel/tools/error: Drop unused MAX_RINGS #define.Kenneth Graunke2017-11-131-2/+0
| | | | | | Dead code. Reviewed-by: Chris Wilson <[email protected]>
* intel/tools/error: Refactor buffer matching, add more buffers.Kenneth Graunke2017-11-131-62/+30
| | | | | | | | | | Based on a similar patch to intel_error_decode by Chris Wilson. While we're de-duplicating the gtt_offset calculation, we can simplify it to assume two hex digits are there - the kernel has done this since v4.6, and we already require error states from v4.10. Reviewed-by: Chris Wilson <[email protected]>
* intel/tools/error: Only decode a few sections of error states.Kenneth Graunke2017-11-131-1/+3
| | | | | | These three are the only we can reasonably decode with genxml. Reviewed-by: Chris Wilson <[email protected]>
* intel/tools/error: Drop unused parameters from decode() helper.Kenneth Graunke2017-11-131-5/+3
| | | | | | | | Also change count from a pointer into a value. We were supposed to be resetting it to 0 (and failed to), but that's gone since we dropped the pre-ascii85 handling. Reviewed-by: Chris Wilson <[email protected]>
* intel/tools/error: Drop support for non-ascii85 encoded error states.Kenneth Graunke2017-11-131-35/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Error state files used to look like: render ring --- gtt_offset = 0x0e8f6000 00000000 : 69040000 00000004 : 79090000 ... 00007ffc : 00000000 --- ringbuffer = 0x00001000 There were thousands of lines between sections. The file format changed with Kernel 4.10, and now has a single ascii85-encoded line following each section heading. This is much easier to parse. There are a bunch of bugs in our handling of the old style format, where we'd decode the wrong data, at the wrong time. Fixing all of these is going to be a giant pain. It's also a lot of extra code complexity. In order to properly decode indirect state, or compute shaders, we'll also need to parse data in advance of decoding, which is going to be a giant pain with this ad-hoc "decode everywhere!" mentality. So, let's just drop support for the older file format. This unfortunately requires an error state generated by Kernel 4.10 or later. That's probably not the end of the world, as we encourage users to upgrade to the latest kernel when encountering GPU hangs anyway. It might be a giant pain for people with LTS kernels, though... Reviewed-by: Chris Wilson <[email protected]>
* intel/tools/error: Do ascii85 decode first.Kenneth Graunke2017-11-131-31/+29
| | | | | | | | | | The dashes "---" may occur within an ascii85 block, but only an ascii85 block starts with ':' or '~'. Ported from Chris Wilson's intel-gpu-tools commit: bceec7e1d8a160226b783c6344eae8cbf4ece144 Reviewed-by: Chris Wilson <[email protected]>
* egl/haiku: Correct invalid void* conversion in callocAlexander von Gluck IV2017-11-131-1/+2
| | | | | Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Eric Engestrom <[email protected]>
* meson: Remove build_by_default from amd codeDylan Baker2017-11-133-3/+3
| | | | | | | This is the same logic as the previous two patches. Signed-off-by: Dylan Baker <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* meson: Don't build intel shared components by defaultDylan Baker2017-11-134-6/+3
| | | | | | | | It's a neat idea, and still useful in some cases, but the intel common code is used by i965 and anvil only, this is a little clearer. Signed-off-by: Dylan Baker <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* meson: don't use build_by_default for specific gallium driversDylan Baker2017-11-1313-34/+25
| | | | | | | | | | | | | | | | | | | Using build_by_default : false is convenient for dependencies that can be pulled in by various diverse components of the build system, the gallium hardware/software drivers and state trackers do not fit that description. Instead, these should be guarded using the variable that tracks whether that driver should be enabled. This leaves a few helper libraries: trace, rbug, etc, and the generic winsys bits as `build_by_default : false` because there are a large number of gallium components that pull them in. v2: - remove build_by_default from winsys convenience libs as well. v3: - Always put drivers before winsys for consistency Signed-off-by: Dylan Baker <[email protected]> Tested-by: Lionel Landwerlin <[email protected]> (v1) Reviewed-by: Eric Anholt <[email protected]>
* r600/shader: handle bitfield extract semantics properly.Dave Airlie2017-11-141-4/+53
| | | | | | | Fixes: tests/spec/arb_gpu_shader5/execution/built-in-functions/fs-bitfieldExtract.shader_test Signed-off-by: Dave Airlie <[email protected]>
* r600: handle bitfieldInsert corner case.Dave Airlie2017-11-141-1/+39
| | | | | | | | | This handles the bits >= 32 corner case in bitfieldInsert. Fixes: tests/spec/arb_gpu_shader5/execution/built-in-functions/fs-bitfieldInsert.shader_test. Signed-off-by: Dave Airlie <[email protected]>
* r600: add gs tri strip adjacency fix.Dave Airlie2017-11-144-5/+62
| | | | | | | | | | | | | | Like radeonsi: generate GS prolog to (partially) fix triangle strip adjacency rotation evergreen hw suffers from the same problem, so rotate the geometry inputs to fix this. This fixes: ./bin/glsl-1.50-geometry-primitive-types GL_TRIANGLE_STRIP_ADJACENCY on evergreen. Signed-off-by: Dave Airlie <[email protected]>
* r600: fix isoline tess factor component swapping.Dave Airlie2017-11-141-0/+7
| | | | | | | | | As per radeonsi, the tess factor components for isolines are reversed. Fixes: tests/spec/arb_tessellation_shader/execution/isoline.shader_test Cc: <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* r600/shader: reserve first register of vertex shader.Dave Airlie2017-11-141-2/+4
| | | | | | | | | | r0 in input into vertex shaders contains things like vertexid, we need to reserve it even if we have no inputs. This fixes a bunch of tessellation piglits. Cc: <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* r600: don't emit atomic save if we have no atomic counters.Dave Airlie2017-11-141-0/+3
| | | | | | | Otherwise we end up emitting the fence. Tested-By: Gert Wollny <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* glx/dri3: Fix passing renderType into glXCreateContextAdam Jackson2017-11-131-1/+2
| | | | | | | | | | Without this, trying to create a GLX_RGBA_FLOAT_TYPE_ARB context would fail, because GLX_RGBA_TYPE would be a mismatch with the fbconfig. Cc: [email protected] Reviewed-by: Tapani Pälli <[email protected]> Reviewed-by: Emil Velikov <[email protected]> Signed-off-by: Adam Jackson <[email protected]>
* glx/drisw: Fix glXMakeCurrent(dpy, None, ctx)Adam Jackson2017-11-131-4/+2
| | | | | | | | | | | This is perfectly legal in GL 3.0+. Fixes piglit/glx-create-context-current-no-framebuffer. Cc: [email protected] Reviewed-by: Tapani Pälli <[email protected]> Reviewed-by: Emil Velikov <[email protected]> Signed-off-by: Adam Jackson <[email protected]>
* glx: Lower GLX opcode lookup into SendMakeCurrentRequestAdam Jackson2017-11-131-9/+7
| | | | | | Reviewed-by: Tapani Pälli <[email protected]> Reviewed-by: Emil Velikov <[email protected]> Signed-off-by: Adam Jackson <[email protected]>
* aubinator: Don't skip the first field in each subgroupJason Ekstrand2017-11-131-2/+3
| | | | | | | | | | The previous iteration algorithm would advance the field pointer right after we advance the group. This meant that you would end up with skipping the first field of the group. In the common case, where the only field is a struct (e.g. 3DSTATE_VERTEX_BUFFERS), it would get skipped entirely. Reviewed-by: Lionel Landwerlin <[email protected]>
* intel/genxml: Delete empty groupsJason Ekstrand2017-11-134-8/+0
| | | | | | | | | They serve no purpose other than to just fill empty space in the packet so each dword has something. Just disallowing empty groups is a bit easier on some of the tools. This does not change the generated packing headers in any way. Reviewed-by: Lionel Landwerlin <[email protected]>
* anv: Don't crash on invalid heap sizes when the PCI ID is overridenJason Ekstrand2017-11-131-0/+12
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* nir/spirv: tg4 requires a samplerAlex Smith2017-11-132-2/+1
| | | | | | | | | | Gather operations in both GLSL and SPIR-V require a sampler. Fixes gathers returning garbage when using separate texture/samplers (on AMD, was using an invalid sampler descriptor). Signed-off-by: Alex Smith <[email protected]> Cc: "17.2 17.3" <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* spirv: Use correct type for sampled imagesAlex Smith2017-11-133-6/+6
| | | | | | | | | | | | | | | | | | | | | | We should use the result type of the OpSampledImage opcode, rather than the type of the underlying image/samplers. This resolves an issue when using separate images and shadow samplers with glslang. Example: layout (...) uniform samplerShadow s0; layout (...) uniform texture2D res0; ... float result = textureLod(sampler2DShadow(res0, s0), uv, 0); For this, for the combined OpSampledImage, the type of the base image was being used (which does not have the Depth flag set, whereas the result type does), therefore it was not being recognised as a shadow sampler. This led to the wrong LLVM intrinsics being emitted by RADV. Signed-off-by: Alex Smith <[email protected]> Cc: "17.2 17.3" <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* spirv: add DO NOT EDIT warning on generated spirv_info.cAlejandro Piñeiro2017-11-131-1/+4
| | | | Reviewed-by: Eric Engestrom <[email protected]>
* loader/dri3: Improve dri3 thread-safetyThomas Hellstrom2017-11-132-18/+69
| | | | | | | | | | | | | | | | | | | | | | | | | It turned out that with recent changes that call into dri3 from glFinish(), it appears like different thread end up waiting for X events simultaneously, causing deadlocks since they steal events from eachoter and update the dri3 counters behind eachothers backs. This patch intends to improve on that. It allows at most one thread at a time to wait on events for a single drawable. If another thread intends to do the same, it's put to sleep until the first thread finishes waiting, and then it rechecks counters and optionally retries the waiting. Threads that poll for X events never pulls X events off the event queue if there are other threads waiting for events on that drawable. Counters in the dri3 drawable structure are protected by a mutex. Finally, the mutex we introduce is never held while waiting for the X server to avoid unnecessary stalls. This does not make dri3 drawables completely thread-safe but at least it's a first step. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102358 Fixes: d5ba75f8881 "st/dri2 Plumb the flush_swapbuffer functionality through to dri3" Signed-off-by: Thomas Hellstrom <[email protected]> Acked-by: Nicolai Hähnle <[email protected]>
* etnaviv: automake,meson: include common_3d.xml.h in the sources listsJuan A. Suarez Romero2017-11-132-0/+2
| | | | | | | v2: include the file also in the meson.build (Eric Engestrom). Fixes: f1e1c60ff6 ("etnaviv: Update from rnndb") Reviewed-by: Eric Engestrom <[email protected]>
* egl: EXT_pixel_format_float plumbingTapani Pälli2017-11-135-0/+15
| | | | | | | | | | | | | | | Patch adds support and capability to match with new surface attribute, component type. Currently no configs with floating point type are exposed. With this change, following dEQP test starts to pass: dEQP-EGL.functional.choose_config.color_component_type_ext.dont_care dEQP-EGL.functional.choose_config.color_component_type_ext.fixed dEQP-EGL.functional.choose_config.color_component_type_ext.float Signed-off-by: Tapani Pälli <[email protected]> Reviewed-by: Eric Engestrom <[email protected]> Reviewed-by: Adam Jackson <[email protected]>
* radv: add unlikely() around radv_save_descriptors()Samuel Pitoiset2017-11-131-1/+1
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: optimize calling radv_cmd_buffer_trace_emit()Samuel Pitoiset2017-11-133-8/+12
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: optimize calling radv_save_pipeline()Samuel Pitoiset2017-11-131-5/+5
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: use vk_zalloc instead of vk_alloc+memsetSamuel Pitoiset2017-11-134-21/+13
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: remove unnecessary memset() in radv_AllocateCommandBuffers()Samuel Pitoiset2017-11-131-3/+0
| | | | | | | | This should not be needed, if the allocation fails an error is returned and the host should handle it. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: remove useless initializations in radv_create_cmd_buffer()Samuel Pitoiset2017-11-131-2/+0
| | | | | | | There is a memset() above. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: remove useless memset() in radv_CreateFence()Samuel Pitoiset2017-11-131-1/+0
| | | | | | | All radv_fence fields are initialized here. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: use vk_error() everywhere an error is returnedSamuel Pitoiset2017-11-138-27/+27
| | | | | | | For consistency and it might help for debugging purposes. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: make radv_emit_framebuffer_state() staticSamuel Pitoiset2017-11-132-3/+2
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: do not emit the framebuffer when restoring a passSamuel Pitoiset2017-11-131-1/+1
| | | | | | | | Instead just dirty RADV_CMD_DIRTY_FRAMEBUFFER and it will be re-emitted if necessary before the next draw. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: prefetch VBO descriptors at the right placeSamuel Pitoiset2017-11-132-0/+21
| | | | | | | | | | | Just after the vertex shader. This seems to give a minor boost for, at least, Serious Sam Fusion 2017 and Dawn of War 3. I don't see any real impacts with The Talos Principle. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: add radv_emit_prefetch_TC_L2_async() helperSamuel Pitoiset2017-11-131-2/+9
| | | | | | | Will be used for VBO descriptors prefetching. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: rename radv_emit_shaders_prefetch() to radv_emit_prefetch()Samuel Pitoiset2017-11-131-6/+6
| | | | | | | | For consistency because this function will also prefetch VBO descriptors. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* glsl/linker: use without_array() to retrieve typeIago Toral Quiroga2017-11-131-3/+4
| | | | | | | | This is what we do in the condition too, so it makes sense. v2: Only compute without_array() once (Ilia). Reviewed-by: Ilia Mirkin <[email protected]>
* radv: emit esgs ring size in one place.Dave Airlie2017-11-132-7/+8
| | | | | | | | | This register is the same on all gpus so far, so emit it in one place and also for the pre-gfx9 gpus set the value in the pipeline creation. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: move calculating vs out info regs into pipeline.Dave Airlie2017-11-133-25/+34
| | | | | | | | This moves some calculations of register values into the pipeline construction, it saves looking at outinfo in the cmd buffer emit. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* freedreno/a5xx: fix SSBO emit for non-zero offsetRob Clark2017-11-121-1/+1
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/a5xx: remove obsolete commentRob Clark2017-11-121-4/+0
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: don't create split/fo if only writing .xRob Clark2017-11-121-0/+6
| | | | | | | In case an instruction only writes one register, and it is .x, we can skip the extra level of fanout indirection. Signed-off-by: Rob Clark <[email protected]>
* freedreno/a5xx: indirect gridsRob Clark2017-11-123-20/+86
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/a5xx: add global size compute capRob Clark2017-11-121-0/+5
| | | | Signed-off-by: Rob Clark <[email protected]>
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