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* amdgpu/addrlib: style changes and minor cleanupsNicolai Hähnle2017-03-3011-84/+82
* amdgpu/addrlib: AddrLib inheritance refactorNicolai Hähnle2017-03-309-560/+675
* amdgpu/addrlib: rearrange code in preparation of refactoringNicolai Hähnle2017-03-305-3528/+3595
* amdgpu/addrlib: add disableLinearOpt flagXavi Zhang2017-03-303-3/+8
* amdgpu/addrlib: Add GetMaxAlignmentsXavi Zhang2017-03-308-1/+184
* amdgpu/addrlib: Let Kaveri go general stereo right eye offset padding pathXavi Zhang2017-03-304-54/+41
* amdgpu/addrlib: Rewrite tile mode optmization codeXavi Zhang2017-03-307-34/+57
* amdgpu/addrlib: Add a flag "tcCompatible" to surface info output structure.Carlos Xiong2017-03-303-15/+50
* amdgpu/addrlib: Make comments shorterXavi Zhang2017-03-301-47/+29
* amdgpu/addrlib: add new flag nonSplitXiaoYuan Zheng2017-03-302-2/+3
* amdgpu/addrlib: allow tileSplitBytes greater than row sizeXiao-Tao Zai2017-03-301-1/+1
* amdgpu/addrlib: Change to compute TC compatible stencil infoCarlos Xiong2017-03-302-65/+59
* amdgpu/addrlib: rename SiAddrLib/CiAddrLib to match internal spellingNicolai Hähnle2017-03-304-149/+149
* st/glsl_to_tgsi: use glsl_type::sampler_index()Samuel Pitoiset2017-03-301-66/+2
* glsl: allow glsl_type::sampler_index() with imagesSamuel Pitoiset2017-03-301-1/+1
* st/mesa: improve error messages and fix security warningNicolai Hähnle2017-03-301-2/+2
* i965: Combine intel_batchbuffer_reloc and intel_batchbuffer_reloc64Kenneth Graunke2017-03-303-53/+19
* i965: Use WARN_ONCE instead of open coding it.Kenneth Graunke2017-03-301-9/+4
* android: pass sse4.1 flag as appropriateHarish Krupo2017-03-301-0/+3
* radv: fix mask attribs properly.Dave Airlie2017-03-301-2/+2
* radv: fix regression with mask attrib setting code.Dave Airlie2017-03-301-3/+3
* radv: move to using nir clip/cull merge pass.Dave Airlie2017-03-302-112/+40
* swr: [scons] Fix windows buildGeorge Kyriazis2017-03-291-7/+31
* anv/cmd_buffer: fix host memory leakCraig Stout2017-03-291-1/+9
* mesa/glthread: fallback to sync if count validation failsTimothy Arceri2017-03-301-8/+14
* mesa/glthread: add async support to glProgramUniform*() functionsTimothy Arceri2017-03-301-34/+34
* mesa/glthread: print out syncs when MARSHAL_MAX_CMD_SIZE is exceededTimothy Arceri2017-03-302-0/+14
* anv/batch_chain: Handle another OOM in cmd_buffer_execbufJason Ekstrand2017-03-291-2/+4
* st/mesa: EGLImageTarget* error handlingPhilipp Zabel2017-03-291-4/+19
* st/mesa: move st_manager_get_egl_image_surface into st_cb_eglimage.cPhilipp Zabel2017-03-293-37/+34
* i965: expose BRW_OPCODE_[F32TO16/F16TO32] name on gen8+Alejandro Piñeiro2017-03-291-0/+9
* mesa: remove dd_function_table::BindProgramMarek Olšák2017-03-296-66/+7
* r200: remove BindProgramMarek Olšák2017-03-292-16/+5
* i915: remove BindProgramMarek Olšák2017-03-291-25/+0
* mesa: don't use _NEW_TEXTURE mainly in mesa/mainMarek Olšák2017-03-295-14/+17
* mesa: split _NEW_TEXTURE into _NEW_TEXTURE_OBJECT & _NEW_TEXTURE_STATEMarek Olšák2017-03-2915-48/+50
* mesa: inline _mesa_update_textureMarek Olšák2017-03-293-22/+14
* mesa: update lower_jumps tests after bug fixTimothy Arceri2017-03-291-2/+15
* gbm/dri: Flush after unmapThomas Hellstrom2017-03-291-1/+8
* radv: Enable sparseBinding feature.Bas Nieuwenhuizen2017-03-291-4/+8
* radv/amdgpu: Use reference counting for bos.Bas Nieuwenhuizen2017-03-292-0/+11
* radv: Implement sparse memory binding.Bas Nieuwenhuizen2017-03-291-4/+80
* radv: Implement sparse image creation.Bas Nieuwenhuizen2017-03-292-2/+22
* radv: Implement sparse buffer creation.Bas Nieuwenhuizen2017-03-292-2/+21
* radv/amdgpu: Add winsys implementation of virtual buffers.Bas Nieuwenhuizen2017-03-294-26/+349
* radv: Assert when setting 0 registers in a sequence.Bas Nieuwenhuizen2017-03-291-0/+4
* anv/cmd_buffer: Refactor flush_pipeline_select_*Jason Ekstrand2017-03-281-26/+16
* anv: Flush caches prior to PIPELINE_SELECT on all gensJason Ekstrand2017-03-281-2/+1
* anv/cmd_buffer: Fix bad indentationJason Ekstrand2017-03-281-24/+25
* anv/cmd_buffer: Apply flush operations prior to executing secondariesJason Ekstrand2017-03-281-0/+5
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