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* r300g: Organize inlined state.Corbin Simpson2009-11-071-36/+36
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* r300g: DCE.Corbin Simpson2009-11-072-27/+2
| | | | This must never have been called before; it's completely wrong.
* r300g: Minor code cleanup to avoid confusion.Corbin Simpson2009-11-071-2/+1
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* r300g: Remove do-nothing functions.Corbin Simpson2009-11-071-12/+0
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* r300g: Remove faulty assert.Corbin Simpson2009-11-071-3/+1
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* Merge branch 'r300g-vbo'Corbin Simpson2009-11-0713-113/+446
|\ | | | | | | | | | | This is an experimental HW TCL fastpath for r300g. It should run alright. Thanks to osiris for making this possible.
| * r300g: Be more verbose in what's killing us WRT vert formats.Corbin Simpson2009-11-071-4/+12
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| * r300g: Comments.Corbin Simpson2009-11-072-6/+11
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| * r300g: Don't assert on oversized VBOs, just return FALSE.Corbin Simpson2009-11-071-4/+12
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| * r300g: Moar vbo cleanup.Corbin Simpson2009-11-071-8/+12
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| * r300g: s/false/FALSE/Corbin Simpson2009-11-072-9/+9
| | | | | | | | Also s/true/TRUE/
| * r300g: Clean up indexbuf render, switch to RELOC macro.Corbin Simpson2009-11-071-15/+17
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| * r300g: Clean up r300_setup_vertex_buffers.Corbin Simpson2009-11-071-15/+13
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| * r300g: Don't pass hw_prim around in the context.Corbin Simpson2009-11-075-81/+74
| | | | | | | | And some other fixes.
| * r300g: Use common state funcs for translating vert formats.Corbin Simpson2009-11-071-72/+6
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| * r300g: don't hang GPU on misbehaving appsMaciej Cencora2009-11-071-0/+6
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| * r300g: VBOs WIPMaciej Cencora2009-11-0710-109/+477
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| * r300g: add missing flushMaciej Cencora2009-11-071-0/+2
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| * r300g: enable CS dumpingMaciej Cencora2009-11-071-2/+2
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| * r300g: move vborender context function to seperate fileMaciej Cencora2009-11-072-1/+6
| | | | | | | | | | | | r300g: Un-migrate r300_draw_render. It'll make maintaining the SW TCL path easier.
* | i915g: Fix comment in is buffer referencedJakob Bornecrantz2009-11-071-7/+3
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* mesa: move code after declbrian2009-11-071-1/+2
| | | | Fixes bug 24967.
* nv50: enable all 32 threads of a warpChristoph Bumiller2009-11-071-1/+3
| | | | | This should be the default setting. See also 7d967b9b7c08aea2a471c5bf6aced8bfafdae874.
* i965: Use Compr4 instruction compression mode on G4X and newer.Eric Anholt2009-11-063-17/+29
| | | | | | | No statistically significant performance difference at n=3 with either openarena or my GL demo, but cutting program size seems like a good thing to be doing for the hypothetical app that has a working set near icache size.
* i965: Share min/max between brw_wm_emit.c and brw_wm_glsl.cEric Anholt2009-11-063-60/+72
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* i965: Share emit_fb_write() between brw_wm_emit.c and brw_wm_glsl.cEric Anholt2009-11-064-127/+40
| | | | This should fix issues with antialiased lines in GLSL.
* i965: Share most of the WM functions between brw_wm_glsl.c and brw_wm_emit.cEric Anholt2009-11-063-297/+109
| | | | | The PINTERP code should be faster for brw_wm_glsl.c now since brw_wm_emit.c's had been improved, and pixel_w should no longer stomp on a neighbor to dst.
* i965: Share math functions between brw_wm_glsl.c and brw_wm_emit.c.Eric Anholt2009-11-063-221/+111
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* i965: Share the sop opcodes between brw_wm_glsl.c and brw_wm_emit.c.Eric Anholt2009-11-063-74/+29
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* i965: Share OPCODE_MAD between brw_wm_glsl.c and brw_wm_emit.cEric Anholt2009-11-063-30/+13
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* i965: Share the DP3, DP4, and DPH between brw_wm_glsl.c and brw_wm_emit.cEric Anholt2009-11-063-99/+33
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* i965: Add generic GLSL code for unaliasing a 3-arg opcode, and share LRP code.Eric Anholt2009-11-063-45/+71
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* i965: Use a normal alu1 emit for OPCODE_TRUNC.Eric Anholt2009-11-062-34/+2
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* i965: Share basic ALU ops between brw_wm_glsl and brw_wm_emit.cEric Anholt2009-11-063-117/+38
| | | | | This drops support for get_src_reg_imm in these, but the prospect of getting brw_wm_pass*.c onto our GLSL path is well worth some temporary pain.
* i965: Collect GLSL src/dst regs up in generic code.Eric Anholt2009-11-062-7/+17
| | | | | | | | This matches brw_wm_emit.c, which we'll be using shortly. There's a possible penalty here in that we'll allocate registers for unused channels, since we aren't doing ref tracking like brw_wm_pass*.c does. However, my measurements on GM965 don't show any for either OA or UT2004 with the GLSL path forced.
* st/xorg: implement batching for the composite opZack Rusin2009-11-064-90/+161
| | | | something is broken so disabled for now
* st/xorg: batch solid fill requestsZack Rusin2009-11-064-95/+66
| | | | | instead of lots of very small transfers, one larger is a lot better for performance
* st/xorg: start accumulating vertices in a common bufferZack Rusin2009-11-062-48/+88
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* st/xorg: use quads instead of triangle fansZack Rusin2009-11-061-4/+4
| | | | easier to split, accumulate and batch those
* st/xorg: make the buffer size globalZack Rusin2009-11-061-1/+9
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* mesa: Reduce the source channels considered in optimization passes.Eric Anholt2009-11-061-1/+40
| | | | | | | Depending on the writemask or the opcode, we can often trim the source channels considered used for dead code elimination. This saves actual instructions on 965 in the non-GLSL path for glean glsl1, and cleans up the writemasks of programs even further.
* mesa: Fix remove_instructions to successfully remove when removeFlags[0].Eric Anholt2009-11-061-0/+6
| | | | | This fixes the dead code elimination to work on the particular code mentioned in the previous commit.
* mesa: Add an optimization path to remove use of pointless MOVs.Eric Anholt2009-11-061-1/+83
| | | | | | | | | | | | | | | | | | GLSL code such as: vec4 result = {0, 1, 0, 0}; gl_FragColor = result; emits code like: 0: MOV TEMP[0], CONST[0]; 1: MOV OUTPUT[1], TEMP[0]; and this replaces it with: 0: MOV TEMP[0], CONST[0]; 1: MOV OUTPUT[1], CONST[0]; Even when the dead code eliminator fails to clean up a now-useless MOV instruction (since it doesn't do live/dead ranges), this should at reduce dependencies.
* mesa: Fix up the remove_dead_code pass to operate on a channel basis.Eric Anholt2009-11-061-28/+56
| | | | | | | This cleans up a bunch of instructions in GLSL programs to have limited writemasks, which would translate to wins in shaders that hit the i965 brw_wm_glsl.c path by depending less on in-driver optimizations. It will also help hit other optimization passes I'm looking at.
* intel: better front color buffer test in intelClear()Brian Paul2009-11-061-2/+3
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* i965: Always pass the size argument to brw_cache_data.Eric Anholt2009-11-066-57/+21
| | | | | This keeps the individual state files from having to export their structures for brw_state_cache initialization.
* intel: Finish removing the fallback code for bug #16697.Eric Anholt2009-11-061-6/+2
| | | | I fixed it properly as of 7216679c1998b49ff5b08e6b43f8d5779415bf54.
* intel: Don't validate in a texture image used as a render target.Eric Anholt2009-11-063-11/+15
| | | | | Otherwise, we could lose track of rendering to that image, which could easily happen during mipmap generation.
* mesa: Attempt to pair up Driver.RenderTexture and FinishRenderTexture()Eric Anholt2009-11-061-0/+4
| | | | | | | | | | This is probably not 100% complete (bind vs unbind may still not pair up exactly), but it should help out drivers which are relying on FinishRenderTexture to be called when we're done rendering to a particular texture level, not just when we're done rendering to the object at all. This is the case for the one consumer of FinishRenderTexture() so far: the gallium state tracker. Noticed when trying to make use of FRT() in the intel driver.
* intel: Clean up some extra struct indirection in finalize.Eric Anholt2009-11-061-2/+1
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